Amplifiers – With control of power supply or bias voltage – With control of input electrode or gain control electrode bias
Reexamination Certificate
2001-06-15
2002-12-24
Lee, Benny (Department: 2817)
Amplifiers
With control of power supply or bias voltage
With control of input electrode or gain control electrode bias
C330S12400D
Reexamination Certificate
active
06498534
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to broadband telecommunications. More particularly, the present invention relates to a Class-AB amplifier for a line driver in a broadband telecommunications system.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a typical circuit structure of a Class-AB amplifier
10
, including a pre-amplifier (pre-amp)
12
, error amplifiers
14
(
14
a
,
14
b
) and
15
(
15
a
,
15
b
), and large-sized output devices
16
(
16
a
-
16
d
) in a closed loop configuration. An input signal is amplified through these three stages. Because of the push-pull nature of the Class-AB amplifier structure, both N-type error amplifiers
14
and P-type error amplifiers
15
are required. In order to achieve a required linearity level of the amplifier for a specific application, typically the open loop gain of the amplifier
10
has to be maximized while maintaining stability. To realize a large open loop gain, the gain of each amplifier stage in the signal path, i.e., the pre-amp gain, the error amplifier gain, and the gain from the output devices, should be maximized as much as possible.
However, the gain of an error amplifier cannot be made arbitrarily large because of offset of the error amplifier, which largely depends on the matching of transistors in the error amplifier. The offset of the error amplifier is statistical in nature and considered random, and varies over process and temperature. Such a random offset of the error amplifier causes a random variation in an offset voltage. Since a quiescent current variation (&Dgr;I
Q
/I
Q
) is proportional to the offset voltage (&Dgr;V) and the gain (A
v
) of the amplifier, a large gain of the amplifier causes a large quiescent current variation, which results in excess power dissipation and/or degraded linearity of the overall amplifier.
The quiescent current is basically the operating supply current of the amplifiers, and is required to bias the internal circuitry (such as output devices) of the amplifiers. Since the quiescent current must be always be supplied whether there is signal applied or not, it adds to the power consumption and power dissipation of the amplifier. Designing for very low quiescent current significantly reduces the power dissipation. However, on the other hand, in order to obtain a low distortion and/or high linearity performance of the amplifier, an additional biasing current (i.e., a larger quiescent current) is typically required for the internal circuitry. In such a case, a large fluctuation in the quiescent current also degrades the linearity of the amplifier.
There are two conventional approaches to solve the offset problem of the error amplifier. A widely adopted approach is to limit the gain of the error amplifier (typically an amplification factor of less than 10) to reduce the quiescent current variation due to a random offset. This approach is effective when the signal bandwidth is low and/or the required linearity level of the amplifier is not high. However, simply limiting the error amplifier gain is not an acceptable solution in the applications where the bandwidth and linearity requirements are more demanding, for example, in broadband communications. In broadband communications, the linearity or signal to noise ratio (SNR) of the amplifier dictates the achievable data rate between a transmitter and a receiver.
The other approach to solve the offset problem of the error amplifier is to monitor the quiescent current of the amplifier and adjust the offset using a quiescent control circuit in negative feedback configuration. This approach has been used in Integrated Services Digital Network (ISDN) applications with moderate linearity level. However, complex hardware is required to realize the quiescent current control circuit.
Accordingly, it would be desirable to reduce the quiescent current variation due to amplifier offset while maintaining a sufficient bandwidth and good linearity of the overall amplifier without adding a complex control circuit.
BRIEF DESCRIPTION OF THE INVENTION
An amplifier circuit having a variable output gain includes an input port for receiving an input signal, an output port for supplying an output signal, a first amplifier coupled between the input port and the output port, and a second amplifier coupled between the input port and the output port. The first amplifier includes a first amplifier path having a first amplification factor, effective when the input signal has a voltage level in a first voltage range, and a second amplifier path having a second amplification factor greater than the first amplification factor, effective when the input signal has a voltage level in a second voltage range, the second voltage range including voltages of a first polarity greater than that in the first voltage range. The second amplifier includes a third amplifier path having the first amplification factor, effective when the input signal has a voltage level in a third voltage range, and a fourth amplifier path having the second amplification factor, effective when the input signal has a voltage level in a fourth voltage range, the fourth voltage range including voltages of a second polarity greater than that in the third voltage range.
REFERENCES:
patent: 4439740 (1984-03-01), Harrington
patent: 5017886 (1991-05-01), Geller
patent: 5729174 (1998-03-01), Dunnebacke et al.
Casier et al., “A 3.3-V, Low-Distortion ISDN Line Driver with a Novel Quiescent Current Control Circuit”, Jul. 1998, IEEE Journal of Solid-State Circuits, vol. 33, No. 7, pp. 1130-1133.
Khorramabadi et al., A Highly Efficient CMOS Line Driver with 80-dB Linearity for ISDN U-Interface Applications:, Dec. 1992, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, pp. 1723-1729.
Kim Chun-Sup
Lee Sang-Soo
Choe Henry
Lee Benny
LSI Logic Corporation
Thelen Reid & Priest LLP
LandOfFree
Amplifier circuit for line driver does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Amplifier circuit for line driver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Amplifier circuit for line driver will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2974829