Amplifier circuit for a physical random number generator and...

Details Amplifier circuit for a physical random number generator and... Amplifier circuit for a physical random number generator and...

2001-02-26

2002-10-22

Pascal, Robert (Department: 2817)

Amplifiers

Sum and difference amplifiers

C330S109000, C330S252000

Reexamination Certificate

active

06469576

ABSTRACT:

This application is based on Japanese Patent Application 2000-054611 filed on Feb. 29, 2000, all the content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an amplifier circuit for very small signals to generate a physical random number and a random number generator using the same.
2. Description of the Related Art
There has been known a random number generating device in which a physical random number is generated using white noise of a Zener diode, an avalanche diode, or the like.
The white noise is a very small signal having an amplitude of about several tens of &mgr;Vrms. When the white noise is used, physically completely randomized signals can be generated. Namely, there are obtained random numbers with high purity or reliability. However, the white noise has small voltage amplitude. To obtain random numbers having amplitude to be used in practices, the white noise must be amplified by an amplifier circuit having an amplification factor of about several hundred.
FIG. 8
shows a prior art example of an amplifier circuit using metal oxide semiconductor (MOS) transistors.
An amplifier circuit A is a differential amplifier circuit. A source terminal S
1
of an MOS transistor
101
a
and a source terminal S
2
of an MOS transistor
101
b
are commonly connected to each other. The source terminals S
1
and S
2
are connected via a current source
2
to ground.
Drain terminals D
1
and D
2
respectively of the MOS transistors
101
a
and
101
b
are connected respectively via load resistors
103
a
an
103
b
to a power source voltage V
DD
. An interconnecting point between the drain terminals D
1
and the load resistor
103
a
is connected to an inverted output terminal TVout−. An interconnecting point between the drain terminals D
2
and the load resistor
103
b
is connected to a non-inverted output terminal TVout+.
Gate terminals G
1
and G
2
respectively of the MOS transistors
101
a
and
101
b
are connected to a non-inverted input terminal TVin+ and an inverted input terminal TVin−, respectively.
The differential amplifier circuit A is a dual-end circuit. In an dual-end amplifier circuit, unlike in a single-end amplifier circuit, the circuit has a symmetric configuration. Therefore, when the power source voltage V
DD
varies, influence thereof appears in the inverted output terminal TVout− and the non-inverted output terminal TVout+. Since the influence of variation in the power source voltage V
DD
cancels each other in differential outputs, the circuit configuration is suitable for the amplification of a very small signal.
FIG. 9
shows an output-versus-input characteristic of the differential amplifier in a graph. The abscissa represents an input voltage Vin (Vin
+
−Vin
−
) and the ordinate represents an output voltage Vout (Vout+, Vout−).
To amplify very small amplitude of a signal, for example, by amplifying white noise of an avalanche diode, even when the transistor
101
a
slightly differs in a characteristic, for example, in a threshold value (Vth) from the transistor
101
b
(FIG.
8
), a problem occurs as follows.
In the amplification of very small amplitude, when the transistors
101
a
and
101
b
are equal in the characteristics to each other and an input offset is zero, the amplifier circuit operates in a range A shown in FIG.
8
. The output-versus-input characteristic is hence a little distorted. However, when a small input offset of only about several millivolts (mV) exists between the transistors
101
a
and
101
b
, the operation range of the amplifier circuit is shifted to a range B shown in FIG.
8
.
When the amplifier circuit operates in the range B in which the output-versus-input characteristic is nonlinear, the output waveform is distorted.
Since the input offset is amplified, like the input signal, by the amplification factor of several hundred to appear in the output signal. Therefore, an output offset becomes a very large value ranging from about several hundred millivolts to about one volt.
Although the circuit is symmetrically constructed, the operation is asymmetric. That is, symmetry between the inverted output and the noninverted output is lost. This is disadvantageous because the operation to cancel influence of the variation in the power source becomes weak and noise of the output signal cannot be reduced.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an amplifier circuit for a physical random number generator and a physical random number generator using the same suitable for amplifying an output voltage from a device or an element of which a signal waveform has very small amplitude.
According to one aspect of the present invention, there is provided an amplifier circuit for a physical random number generator for amplifying a very small signal to generate a physical random number signal comprising a pair of first differential input terminals including a first non-inverted input terminal and a first inverted input terminal, a pair of second differential input terminals including a second non-inverted input terminal and a second inverted input terminal, a differential amplifying section for receiving signals respectively from said pairs of first and second differential input terminals and for producing differential output signals in a form of a linear combination of the signals and a first inverted output terminal and a first non-inverted output terminal to output the differential output signals.
According to one aspect of the present invention, there is provided a physical random number generator, comprising said amplifier circuit for a physical random number generator according to claim
1
and physical random number generating means connected to either one of said second non-inverted input terminal and said second inverted input terminal of amplifier circuit for a physical random number generator.
According to one aspect of the present invention, there is provided an amplifier circuit for a physical random number generator for amplifying a very small signal to generate a physical random number signal comprising a pair of first differential input terminals including a first non-inverted input terminal and a first inverted input terminal, a pair of second differential input terminals including a second non-inverted input terminal and a second inverted input terminal, a cascade connection of at least two differential amplifying sections, each of said two differential amplifying section receiving signals respectively from said first and second differential input terminals and producing differential output signals in a form of a linear combination of the signals, and a first inverted output terminal and a first non-inverted output terminal for outputting final differential output signals obtained through said cascade connection of at least two differential amplifying sections.
According to the present invention, there can be provided an amplifier circuit for a physical random number generator and a physical random number generator using the same in which in amplification of an output signal from a physical random number generator device, a signal component is amplified with a sufficiently high amplification factor and a low-frequency component including a direct-current (DC) component such as an offset is amplified with a lower amplification factor.


REFERENCES:
patent: 5570221 (1996-10-01), Fujita
patent: 5706218 (1998-01-01), Hoffman
patent: 5736899 (1998-04-01), Bowers et al.
patent: 5796301 (1998-08-01), Tanabe et al.
patent: 5838197 (1998-11-01), Tsukuda
patent: 5880634 (1999-03-01), Babanezhad
patent: 5892609 (1999-04-01), Saruwatari
patent: 5955918 (1999-09-01), Uno
Hirose et al, “Instanteous-response, adjustment-free, 156Mbit/s limiting amplifier IC for burst-mode optical transmission”, Electronics Letters, IEE Stevenage, GB, vol. 33, No. 2, Jan. 16, 1997, pp 151-152.

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