Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-02-11
2004-01-06
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
Reexamination Certificate
active
06674328
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a amplifier circuit for conducting amplification by using one or more differential amplifier circuits. Particularly this invention relates to an amplifier circuit that compensates an offset voltage caused by, for example, dispersion of transistor characteristics.
BACKGROUND ART
Amplifier circuits used in optical communication systems have multi-stage connected differential amplifier circuits in order to amplify a wide band signal ranging from low frequencies to high frequencies. These differential amplifier circuits are integrated in order to reduce the size and cost. In such integrated circuits, dispersion generating due to transistors cannot be neglected. In other words, a direct current component of a voltage input to a positive-phase input terminal of a differential amplifier circuit is deviated from a direct current component of a voltage input to an negative-phase input terminal due to variations of the temperature and power supply voltage, resulting in an offset voltage. This offset voltage is amplified by the multi-stage differential amplifier circuit, causing a duty variation between the positive-phase and the negative-phase. This causes a problem that a desired output amplitude cannot be obtained.
Japanese Patent Application Laid-Open No. 11-4265 discloses an amplifier that solves the above-mentioned problem.
FIG. 5
is a diagram showing a configuration of this conventional amplifier. This amplifier includes a differential amplifier circuit
83
, which receives an input signal fed from an input terminal
81
as a positive-phase input thereof, and which outputs a positive-phase signal and a negative-phase signal respectively to output terminals
85
and
86
. Moreover, there are provided a peak detector circuit
87
, which receives the negative-phase output of the differential amplifier circuit
83
as an input thereof, and a differential amplifier circuit
89
, which receives an output signal of the peak detector circuit
87
as a negative-phase thereof, receives a reference voltage
90
serving as a linear operation upper limit voltage of the output signal of the differential amplifier circuit
83
as a positive-phase input thereof, and supplies an output thereof to the differential amplifier circuit
83
as its negative-phase input. The differential amplifier circuit
89
forms an offset compensation voltage generator circuit
88
. The input signal supplied from the input terminal
81
is supposed to be a rectangular signal of “1”and “0.”
The differential amplifier circuit
83
amplifies the input signal fed from the input terminal
81
, and outputs the positive-phase signal and the negative-phase signal to the output terminals
85
and
86
, respectively. The peak detector circuit
87
is supplied with the negative-phase output signal fed from the differential amplifier circuit
83
. The peak detector circuit
87
detects a peak voltage of the negative-phase output signal, which corresponds to “0” of the input signal. The differential amplifier circuit
89
detects an offset voltage on the basis of the reference voltage
90
serving as the linear operation upper limit voltage of the output signal and the peak voltage detected by the peak detector circuit
87
, generates an offset compensation voltage by inverting the polarity of the detected offset voltage, and feeds back the generated offset compensation voltage to the differential amplifier circuit
83
. As a result, the offset voltage can be automatically compensated.
By providing the offset compensation voltage generator circuit
88
with a gain, the offset voltage can be further reduced. Denoting an offset voltage generated in the output of the differential amplifier circuit
83
by V
OFFOUT
, an offset voltage contained in the input signal of the differential amplifier circuit
83
by V
OFFIN
, an offset compensation voltage fed back to the differential amplifier circuit
83
by &Dgr;V, and a gain of the differential amplifier circuit
83
by G1, the offset voltage V
OFFOUT
is represented by the following equation (1).
V
OFFOUT
=(
V
OFFIN
−&Dgr;V
)·
G
1 (1)
Denoting a detection efficiency of the peak detector circuit
87
by &eegr;, and again of the offset compensation voltage generator circuit
88
by “G2,” the offset compensation voltage &Dgr;V is represented by the following equation (2).
&Dgr;
V=V
OFFOUT
·&eegr;·G
2 (2)
By substituting the equation (2) into the equation (1) and rewriting a resultant equation, the offset voltage V
OFFOUT
is represented by the following equation (3).
V
OFFOUT
=(
G
1/(1+
G
1
·&eegr;·G
2))·
V
OFFIN
(3)
Supposing (G1·&eegr;·G2)>>1, the equation (3) can be represented as equation (4).
V
OFFOUT
≈(1/(&eegr;·
G
2))·
V
OFFIN
(4)
For example, in the case where &eegr;=0.5 and G2=30 dB, it follows that V
OFFOUT
≈(1/16)·V
OFFIN
. The offset voltage generated in the output of the differential amplifier circuit
83
is thus reduced.
According to the above-described conventional technique, however, the offset compensation voltage generated by the offset compensation voltage generator circuit is fed back to the differential amplifier circuit as it is. This results in a problem that an excessive offset compensation voltage is fed back and consequently stable offset compensation cannot be conducted in some cases. For example, if the amplitude of the input signal exceeds the linear operation range of the differential amplifier circuit, resultant saturation of the peak detection value hinders an accurate offset compensation voltage from being generated, disadvantageously resulting in occurrence of an unstable feedback operation.
Especially, when the offset compensation voltage generation circuit is provided with a gain for reducing the offset voltage, an excessive offset compensation voltage is disadvantageously fed back for the offset voltage that has actually occurred in the output. Furthermore, if the differential amplifier circuit is an equalization amplifier circuit, a large amplitude signal input lowers the gain of the equalization amplifier circuit, and consequently the gain of the offset compensation voltage generator circuit becomes dominant in the feedback loop, and an excessive offset compensation voltage is disadvantageously fed back for the offset voltage that has actually occurred in the output.
It is an object of the present invention to provide an amplifier circuit that makes it possible to limit an excessive offset compensation voltage and conduct stable offset compensation.
DISCLOSURE OF THE INVENTION
The amplifier circuit according to this invention comprises a differential amplifier unit which includes one or more differential amplifier circuits; a detector unit which detects a peak value of an output voltage of the differential amplifier unit; a generator unit which generates an offset compensation voltage for offset compensation based on a detection result of the detector unit; and a limiter unit which limits the offset compensation voltage generated by the generator unit into a predetermined range and feeding back the limited offset compensation voltage to the differential amplifier unit.
According to the above-mentioned invention, the differential amplifier unit conducts amplification, and the detector unit detects a peak value of an output voltage of the differential amplifier unit. The generator unit generates an offset compensation voltage for offset compensation on the basis of a detection result of the detector unit, and the limiter unit limits the offset compensation voltage generated by the generator unit into a predetermined range and feeds back the limited offset compensation voltage to the differential amplifier unit. As a result, the offset compensation voltage fed back to the differential amplifier unit can be limited into a predetermined range.
In the above-mentioned amplifier circuit according to this invention, the limiter unit generates a bias voltage of the differential amplifier unit.
Thus, since
Motoshima Kuniaki
Uto Ken-ichi
Mitsubishi Denki & Kabushiki Kaisha
Mottola Steven J.
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