Amplifier circuit

Details Amplifier circuit Amplifier circuit

2000-09-08

2002-03-19

Shingleton, Michael B (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S260000

Reexamination Certificate

active

06359510

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a fully differential type amplifier circuit using a differential difference amplifier (DDA).
2. Description of the Related Background Art
Conventionally, in order to form a non-inverting amplifier having large input impedance, a technique based on a fully differential type (balanced type) DDA is employed. The balanced type DDA is shown in a symbolic diagram of FIG.
1
and in a circuit diagram of FIG.
2
. This DDA
1
includes: a differential input stage
11
comprising NMOS transistors Q
1
, Q
2
and Q
13
; a differential input stage
12
comprising NMOS transistors Q
3
, Q
4
and Q
15
; an output stage
13
having a PMOS transistor Q
11
and an NMOS transistor Q
14
; an output stage
14
having a PMOS transistor Q
12
and an NMOS transistor Q
16
; four input terminals VPP, VPN, VNP and VNN; and two output terminals VoutP and VoutN.
Between the output terminals VoutN and VoutP, a common mode feedback circuit
15
is provided. The common mode feedback circuit
15
controls the gate voltages of PMOS transistors Q
5
and Q
6
which are used as common loads to the two differential input stages
11
and
12
. The connection node of the transistors Q
5
, Q
2
and Q
3
controls the gate of one output stage transistor Q
12
, and the connection node of the transistors Q
6
, Q
4
and Q
1
controls the gate of the other output stage transistor Q
11
.
A resistor R
11
and a capacitor C
11
, which are provided between the gate and drain of the output stage transistor Q
11
, constitute a phase compensator circuit. Similarly, a resistor R
12
and a capacitor C
12
, which are provided between the gate and drain of the output stage transistor Q
12
, constitute a phase compensator circuit. The NMOS transistors Q
13
through Q
16
are current source transistors for controlling a bias current for each of the differential input stages
11
and
12
, and are controlled by a voltage Vbias which is applied from the outside of the circuit.
The common mode feedback circuit
15
is designed to carry out a negative feedback control for suppressing a output common mode component. For example, the common mode feedback circuit
15
is formed as shown in FIG.
3
. The common mode feedback circuit
15
of
FIG. 3
includes: a differential input stage comprising NMOS transistors Q
21
, Q
22
and Q
23
; and a load circuit comprising PMOS transistors Q
24
and Q
25
which are diode-connected. The gate of one transistor Q
21
of the differential input stage is connected to output terminals VoutN and VoutP via resistors R
21
and R
22
, respectively. By these resistors R
21
and R
22
, a common mode component contained in output signals VoutN and VoutP of the balanced type DDA
1
is detected. This is compared with a reference voltage VAG applied to the gate of the other transistor Q
22
and a control signal VC is generated. By this control signal VC, the negative feedback control of the DDA
1
is carried out, so that the output common mode voltage is substantially equal to the VAG.
In such a balanced type DDA
1
having four inputs and two outputs, the output signal of one output terminal VoutP has a positive gain with respect to an input signal of a difference between the input terminal VPP and the input terminal VPN, and the output signal of the other output terminal VoutN has a negative gain with respect thereto. In addition, one output terminal VoutP has a negative gain with respect to an input signal of a difference between the input terminal VNP and the input terminal VNN, and the other output terminal VoutN has a positive gain with respect thereto. These gains are determined by a product of the gain of the differential input stage by the gain of the output stage. Assuming that the mutual conductance of the MOS transistors Q
1
, Q
2
, Q
3
and Q
4
is gm, the drain-to-source conductance is gdsn, and the drain-to-source conductance of the MOS transistors Q
5
and Q
6
is gdsp, then, the gain of the differential input stage with respect to the differential input signal is gm/(gdsn+gdsp). Therefore, it can be seen that the mutual conductance of the differential transistor pair of the differential input stage is in proportion to the absolute value of the gain of the DDA
1
. Using such a balanced type DDA
1
, a non-inverting amplifier circuit is formed as shown in FIG.
4
. This circuit comprises resistors R
1
through R
3
in addition to the balanced type DDA
1
, and outputs VoutP and VoutN with respect to VinP and VinN. Since a negative feedback is applied to the circuit by the resistors R
1
through R
3
, the operation of this non-linear amplifier circuit satisfies the following formula (1) assuming that the gain of the balanced type DDA
1
is infinity.
(
VPP−VPN
)−(
VNP−VNN
)=0  (1)
Therefore, assuming that the resistance value of the resistor R
3
is Ra and that the resistance value of the resistors R
1
and R
2
is Rb, the gain A of this circuit is expressed by the following formula (2).
A={Rb+
(
Ra/
2)}/(
Ra/
2)  (2)
Assuming that the common mode component of the input voltages VinP and VinN is VCMi, the differential component thereof is Vi, the common mode component of the output voltages VoutP and VoutN is VCMO, and the differential output component thereof is Vo, then, the following relationships (3) through (7) are established.
VPP=VCMi+Vi
  (3)
VNP=VCMi−Vi
  (4)
V
out
P=VCMO+Vo
  (5)
V
out
N=VCMO−Vo
  (6)
Vo=A·Vi
  (7)
Since the input terminal of the balanced type DDA
1
is connected to the gate of the MOS transistor as shown in
FIG. 2
, no current flows into the input terminal in principle. Therefore, VPN and VNN are determined by the resistors R
1
through R
3
and the output voltages VoutP and VoutN as shown in the following formulae (8) and (9).
 
VPN=VAG+Vi
  (8)
VNN=VAG−Vi
  (9)
If VCMi≠VCMO, then VPP≠VPN and VNP≠VNN. That is, if the common mode component VCM of the input voltage of the DDA
1
is different from the common mode component VCMO of the output voltage, two signals inputted to the differential input stage have different voltages.
Referring to
FIGS. 5 and 6
, the operation of the differential input stage will be considered. The differential input stage of
FIG. 5
comprises NMOS transistors Q
51
, Q
52
and Q
53
. The gate potential of the NMOS transistor Q
53
is controlled by a voltage Vbias so as to flow a desired bias current Ibias. It is herein assumed that the gate-to-source voltage of the MOS transistor Q
51
is VGS
1
, the drain current thereof is ID
1
, the gate-to-source voltage of the MOS transistor Q
52
is VGS
2
, and the drain current thereof is ID
2
. Assuming that the characteristics of the MOS transistors Q
51
and Q
52
can be expressed by ID=K (VGS−VTH)
2
using a gate-to-source voltage VGS, a drain current ID, a threshold voltage VTH and a mutual conductance parameter K, then, the relationship between &Dgr;Vi=VGS
1
−VGS
2
and &Dgr;ID=ID
1
−ID
2
is expressed by the following formula (10).
&Dgr;ID=&Dgr;Vi·K
{2
Ibias/K−
(&Dgr;
Vi
)
2
}
½
  (10)
The relationship of the formula (10) is shown in FIG.
6
. It can be seen from this figure that a range (a linear operation range of a differential input stage), in which &Dgr;ID varies substantially linearly with respect to &Dgr;Vi, is inversely in proportion to K. If this range is not sufficiently large as compared with the difference between the voltages of two signals inputted to the differential input stage, distortion occurs.
Therefore, it is conventionally designed that the linear operation range of the differential input stage is sufficiently large. Assuming that the channel width of the MOS transistor is W and the channel length thereof is L, K is in proportion to W/L, so that the linear operation r

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