Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2011-03-01
2011-03-01
Choe, Henry K (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
C330S285000
Reexamination Certificate
active
07898339
ABSTRACT:
An amplifier circuit with favorable linearity is provided.An amplifier of the present invention is provided with an amplifier MOS transistor, a diode-connected transistor block for negative feedback source impedance constituted by series-parallel connection of the limited number (including 0) of the diode-connected MOS transistors and connected to a source side of the amplifier MOS transistor, and a diode-connected transistor block for load constituted by series-parallel connection of the limited number of the diode-connected MOS transistors and connected to a drain side of the amplifier MOS transistor. A voltage gain is configured to be determined by a ratio of the sum of source impedance of the amplifier MOS transistor and the impedance of the diode-connected transistor block for negative feedback source impedance to the impedance of the diode-connected transistor block for load.
REFERENCES:
patent: 7151410 (2006-12-01), Franck et al.
patent: 7541875 (2009-06-01), Taylor et al.
patent: 7551036 (2009-06-01), Berroth et al.
patent: 7629851 (2009-12-01), Tsurumaki et al.
patent: 2007-248202 (2007-09-01), None
Ikeda Masato
Miyashita Tokio
Choe Henry K
Kabushiki Kaisha Nihon Micronics
NES Co., Ltd
Turocy & Watson LLP
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