Amplifier circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307270, 307DIG1, 307DIG4, 307DIG5, H03K 3286, H03K 3353

Patent

active

039873153

ABSTRACT:
An amplifier circuit for amplifying an input signal includes a flip-flop circuit activated by a timing signal. A trigger circuit generates a first trigger signal of the same polarity as the input signal and another circuit generates a second trigger signal of the opposite polarity to the input signal. The flip-flop circuit is triggered by the first and second trigger signals at the same time the flip-flop circuit is activated by the timing signal.

REFERENCES:
patent: 3614476 (1971-10-01), Teranishi
patent: 3697775 (1972-10-01), Kane
patent: 3801831 (1974-04-01), Dame
patent: 3840757 (1974-10-01), Nomiya et al.
patent: 3902082 (1975-08-01), Proebsting et al.
patent: 3916430 (1975-10-01), Heuner et al.
patent: 3917960 (1975-11-01), Kane
patent: 3922647 (1975-11-01), Broeker, Jr.
kraft et al., "Low-Power Gated FET Latch"; IBM Tech. Discl. Bull.; vol. 15, No. 7, p. 2280; 12/1972.
Chin et al., "Low-Power Data Register"; IBM Tech. Discl. Bull.; vol. 15, No. 12, pp. 3891-3892; 5/1973.

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