Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2002-11-13
2004-11-16
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
Reexamination Certificate
active
06819185
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of electronics. More particularly, the invention relates to amplifier biasing.
BACKGROUND
In amplifier design, a biasing circuit or network is intended to set and maintain the direct current (DC) bias point for the amplifier, allowing an amplifier to operate at an appropriate point in the amplifier's transfer characteristic. A bias network is intended to provide bias stability when there are variations in input signals, circuit parameters, or circuit conditions. The biasing circuit used for an amplifier will have significant effect on the operation of the amplifier.
However, conventional bias networks do not address all issues in amplifier operation and may not provide a DC bias point that is sufficiently stable and accurate under all circumstances. A conventional bias network may not sufficiently inhibit large signal de-biasing of the amplifier. Further, conventional bias networks may allow significant power gain variations as a function of input power, in which the power gain compresses as the input power is increased.
FIG. 1
is an illustration of a conventional bias network that may be used in a radio frequency (RF) power amplifier. Transistors Q
1
125
and Q
3
135
make up a simple current mirror reference for an RF power transistor Q
2
170
. I
b
115
is a current source coupled between the current mirror and voltage source V
CC
185
. The bias current for Q
2
is provided by diode Q
4
140
and resistor R
2
145
, with stability of the bias network being provided by dominant pole capacitor C
3
120
. For stability, a capacitor across R
3
130
is sometimes also needed to provide feed-forward compensation. Resistor R
1
150
is intended to provide RF isolation of the bias network and prevent loading of the input
105
. The input is alternating current (AC) coupled to the base of transistor Q
2
170
via capacitor C
2
155
.
In
FIG. 1
, the output collector of Q
2
170
is biased with inductor L
c
160
, the other end of inductor L
c
160
being coupled to voltage source V
CC
185
. The output port
110
will typically drive a 50-Ohm matching network. The emitter inductor L
c
175
shown between the emitter of Q
2
170
and ground
180
represents the package impedance, the inductance created by typical package ground impedance and/or bond wires. Resistor R
3
130
is inserted between the base of Q
1
125
and the emitter of Q
3
135
to provide base current compensation. The voltage drop across R
1
is the base current error voltage V
err
=I
b2
×R
1
, where I
b2
is the base current of Q
2
170
. To compensate for this error voltage, the drop across R
3
should be equal to V
err
when the collector current of Q
2
, I
c2
165
, is equal to a given multiple of the collector current of Q
1
I
c1
190
, I
c2
=M×I
c1
. To provide such current at this point, the resistance of R
3
should be equal to the multiple of the resistance of R
1
, R
3
=M×R
1
.
The conventional bias network shown in
FIG. 1
may provide stabilization of the DC bias point as a function of certain factors such as temperature and process variation, but such network does not operate to prevent de-biasing when large signals are imposed on the input port. This failure is due to non-linear rectification effects that occur as the output transistor Q
2
170
transitions from small signal or Class A mode to large signal or Class B mode. The de-biasing effect also causes the power gain to compress (drop in value) at a lower input power level as the bias point sags. A further complication of the de-biasing effect with conventional biasing occurs in circuit design, in which long, time-consuming transient simulations may be needed to determine the final steady state, large signal response. The slow simulation process is the result of the slow settling time of the steady state bias point in operations with the conventional bias network.
REFERENCES:
patent: 5216379 (1993-06-01), Hanley
patent: 5654672 (1997-08-01), Bailey et al.
patent: 5923217 (1999-07-01), Durec
Schilling et al., Electronic Circuits Discrete and Integrated, 2ndedition, McGraw-Hill 1979 pp. 361-162.
Blakeky Sokoloff Taylor & Zafman LLP
Cypress Semiconductor Corporation
Mottola Steven J.
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