Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2000-08-29
2002-08-27
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
C323S314000, C323S315000, C323S316000, C330S288000, C330S295000, C330S296000
Reexamination Certificate
active
06441687
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to RF power amplifiers, and in particular to an amplifier bias voltage generating circuit and method.
BACKGROUND OF THE INVENTION
Radiofrequency power amplifiers are often used in portable applications such as cellular telephones. In these applications, operating voltages are limited by available battery voltage. This low voltage operation presents performance challenges to RF power amplifiers.
In power amplifiers, the bias voltage and current provided to the base of the amplifying transistor(s) determine the class of operation and the linearity of the amplifier response. As standard supply voltages are lowered, conventional current mirror reference circuits that have low output impedance are particularly sensitive to any variations in supply voltage, such as a decrease in supply voltage as the battery is discharged. For obvious reasons, this reference current sensitivity to the supply voltage level is undesirable.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for an amplifier biasing scheme that addresses the disadvantages and deficiencies of the prior art. In particular, a need has arisen for a reference current-dependent bias voltage generating circuit with reduced dependence on the voltage supply level.
Accordingly, a novel bias voltage generating circuit is disclosed. In one embodiment, the bias voltage generating circuit includes a first transistor with a base terminal coupled to the output node and an emitter terminal coupled to ground. The circuit also includes a first resistance with a first terminal coupled to a supply voltage node and a second terminal coupled to a collector terminal of the first transistor. A second transistor has an emitter terminal coupled to the collector terminal of the first transistor and a base terminal connected to the collector terminal of the second transistor. A second resistance has a first terminal coupled to the supply voltage node and a second terminal coupled to a collector terminal of the second transistor. A third transistor has a base terminal coupled to the base terminal of the second transistor, a collector terminal coupled to the supply voltage node, and an emitter terminal coupled to the output node.
In accordance with another aspect of the present invention, a method for amplifying an RF input signal is disclosed. In one embodiment, the method includes providing a supply voltage to a first terminal of a first resistor, where the first resistor has a second terminal coupled to a collector terminal of a first transistor. The method also includes providing the supply voltage to a first terminal of a second resistor, where the second resistor has a second terminal connected to a collector terminal of a second transistor. The second transistor has an emitter terminal coupled to the collector terminal of the first transistor, and a base terminal connected to the collector terminal of the second transistor. The method also includes providing the supply voltage to a collector terminal of a third transistor. The third transistor has a base terminal connected to the base terminal of the second transistor, and an emitter terminal coupled to the base terminal of the first transistor. Finally, the method includes generating a bias voltage by the third transistor at the emitter terminal of the third transistor, supplying the bias voltage to a bias node coupled to a base terminal of an amplifying transistor, supplying the RF input signal to an input node coupled to the base terminal of the amplifying transistor, and amplifying the RF input signal by the amplifying transistor.
An advantage of the present invention is that the bias voltage generating circuit described herein utilizes a larger portion of available supply voltage for sensing current than conventional emitter follower bias circuits, and is therefore much less sensitive to supply voltage changes than conventional bias circuits.
REFERENCES:
patent: 5311148 (1994-05-01), Brannon et al.
patent: 6064268 (2000-05-01), Felps
patent: 6194967 (2001-02-01), Johnson et al.
Shingleton Michael B
Skjerven Morrill & MacPherson LLP
Stewart Daniel P.
TriQuint Semiconductor Inc.
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