Amplifier bias circuit and method

Details Amplifier bias circuit and method Amplifier bias circuit and method

1996-07-01

1998-05-26

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

330277, H03F 316

Patent

active

057572364

ABSTRACT:
A resistor network bias circuit (24) and method is suitable for use in monolithic circuits. The method involves selecting resistors set a quiescent current for a two-stage power amplifier. The bias circuit (24) offsets the gate voltage for a first transistor (14) and a second N-channel depletion mode MESFET transistor (22) to maintain substantially constant drain current for the power amplifier over a range of threshold voltages. Selectable metal links (33-83) serially connected to resistors (30-80) provide parallel resistor combinations (36-86) for setting the quiescent currents of transistors (14 and 22).

REFERENCES:
patent: 3870967 (1975-03-01), Wisseman
patent: 4150366 (1979-04-01), Price
patent: 4194164 (1980-03-01), Owen
patent: 4207538 (1980-06-01), Goel
patent: 4387346 (1983-06-01), Fackler
patent: 5278517 (1994-01-01), Fujita
patent: 5506544 (1996-04-01), Staudinger et al.

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