Amplifier array termination

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C341S159000, C341S158000

Reexamination Certificate

active

06822600

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to analog-to-digital conversion, and, in particular, to a circuit and method of terminating an amplifier array in a folding or a flash type analog-digital-converter for temperature stability.
BACKGROUND
An analog-digital-converter (ADC) is employed to change/convert an analog input signal into a digital output signal. There are several different types of ADC architectures in current use, including pipeline, flash and folding. In a flash ADC, k bits of resolution employ 2
k
comparators to convert an analog signal into a digital signal. Folding ADCs are a variation of a typical flash ADC architecture except that they are arranged to map the analog input signal range into N regions where each of these N regions share the same comparators. In a folding ADC, the total number of comparators is typically 2
k
/N+(N−2).
Flash and folding ADCs may be scaled to very high conversion speeds, since they do not use decision feed-back loops. These two architectures, unfortunately, can be sensitive to device mismatch, leading to linearity degradation. This is especially true of CMOS folding ADCs, since CMOS devices have larger offsets than bipolar devices.
Thus, it is with respect to these considerations and others that the present invention has been made.


REFERENCES:
patent: 6072416 (2000-06-01), Shima
patent: 6100836 (2000-08-01), Bult
patent: 6369732 (2002-04-01), Liu et al.

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