Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2007-07-25
2011-12-27
Mottola, Steven J (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
Reexamination Certificate
active
08085092
ABSTRACT:
An amplifier arrangement comprises a first transistor (18), a first bias transistor (13) and a first field-effect transistor (51). A first input signal (VN) is supplied for amplification to a control terminal of the first transistor (18). The first bias transistor (13) is coupled to the first transistor (18) via a first node (12). The first field-effect transistor (51) is coupled for clamping of a first node voltage (V1) provided at the first node (12).
REFERENCES:
patent: 4427903 (1984-01-01), Sugimoto
patent: 4675594 (1987-06-01), Reinke
patent: 4931718 (1990-06-01), Zitta
patent: 5053718 (1991-10-01), Graeme et al.
patent: 5212458 (1993-05-01), Fitzpatrick et al.
patent: 5502410 (1996-03-01), Dunn et al.
patent: 5963085 (1999-10-01), Sauer
patent: 5973561 (1999-10-01), Heaton
patent: 6525607 (2003-02-01), Liu
patent: 6586980 (2003-07-01), Callahan, Jr.
patent: 6747514 (2004-06-01), Aude
patent: 6768371 (2004-07-01), Layton et al.
patent: 7196555 (2007-03-01), Taylor
patent: 7453247 (2008-11-01), de Cremoux
patent: 2004/0113696 (2004-06-01), Forejt et al.
patent: 2006/0017504 (2006-01-01), Deval et al.
patent: 2008/0048738 (2008-02-01), Singnurkar
patent: 33 45 045 (1984-06-01), None
patent: 0 715 239 (1996-06-01), None
patent: 1 884 856 (2008-02-01), None
patent: 1 921 747 (2008-05-01), None
C.Y. Leung et al., “A 1-V Integrated Current-Mode Boost Converter in Standard 3.3/5-V CMOS Technologies”, IEEE Journal of Solid-State Circuits, vol. 40, No. 11, pp. 2265-2274, Nov. 2005.
D.M. Binkley et al., “Micropower, 0.35 μm/m partially depleted SOI CMOS preamplifiers having low white and flicker noise”, 2003 IEEE Int'l. SOI Conference Proceedings, Newport Beach, CA, Sep. 29-Oct. 2, 2003, IEEE Int'l. SOI Conference, New York, NY:IEEE, U.S., Sep. 29, 2003, pp. 85-86.
T. Fukumoto et al., “Optimizng Bias-circuit Design of Cascode Operational Amplifier for Wide Dynamic Range Operations”, Proceedings of the 2001 Int'l. Symposium on Low Power Electronics and Design, ISLPED, Huntington Beach, CA, Aug. 6-7, 2001, Int'l. Symposium on Low Power Electronics and Design, New York, NY: ACM, U.S., Aug. 6, 2001, pp. 305-309.
Y. Wang et al., “A 3-V High-Bandwidth Integrator for Magnetic Disk Read Channel Continuous-Time Filtering Applications”, Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998 Santa Clara, CA, USA, May 11-14, 1998, New York, NY, USA, IEEE U.S., May 11, 1998, pp. 427-430.
G.A. Rincón-Mora, et al., “Accurate and Lossless Current-Sensing Techniques for Power Applications—A Practical Myth?”, Power Management Design Line, dated Mar. 16, 2005.
C.Y. Leung et al., “An Integrated CMOS Current-Sensing Circuit for Low-Voltage Current-Mode Buck Regulator”, IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 52, No. 7, pp. 394-397, Jul. 2005.
austriamicrosystems AG
Cozen O'Connor
Mottola Steven J
LandOfFree
Amplifier arrangement and method for amplification does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Amplifier arrangement and method for amplification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Amplifier arrangement and method for amplification will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4257236