Amplifiers – With semiconductor amplifying device – Integrated circuits
Reexamination Certificate
2003-02-28
2004-12-21
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Integrated circuits
C330S302000
Reexamination Certificate
active
06833761
ABSTRACT:
BACKGROUND
FIG. 1
illustrates a power amplifier device as is known in the art. The prior art power amplifier device includes a power divider
101
to receive an input signal, a plurality of data flow paths, and a power combiner
116
to provide an output signal.
One data flow path illustrated in
FIG. 1
comprises input impedance matching structure
104
, amplifying device
108
, and output impedance matching structure
112
. The amplifying device
109
is typically a transistor device that amplifies a received signal. Data flows through conductive elements
102
,
106
,
110
, and
114
to create a data flow path from the power divider
101
to the power combiner
116
.
Another data flow path, analogous to the first data path, includes input impedance matching structure
105
, amplifying device
109
, and output impedance matching structure
113
. Data flows through conductive elements
103
,
107
,
111
, and
115
connect the various data flow elements to create a second data flow path from the power divider
101
to the power combiner
116
. While only two data flow paths are indicated in
FIG. 1
, it will be appreciated that other power amplifiers can contain additional data flow paths, or only one data flow path.
The output impedance matching structures
112
in combination with the conductive elements
110
are implemented to realize an output load line structure to allow for partial impedance matching between the amplifying device
108
and the signal out node.
The structure illustrated in
FIG. 1
has an inherent disadvantage in that there is a strong intra-dependence between the fundamental and harmonic frequency terminations exhibited by this circuitry. This strong intra-dependence limits the ability to select design parameters which can simultaneously optimize both the fundamental frequencies, and the harmonic frequencies. The inability to optimize both fundamental and harmonic frequencies prevents class F operation, or near class-F operation, of the device. Therefore, a device and/or method overcoming this problem would be advantageous.
FIELD OF THE INVENTION
The present disclosure relates generally to power amplifiers, and more particularly to power amplifiers having load line structures with harmonic frequency termination structures.
REFERENCES:
patent: 6127894 (2000-10-01), Alderton
patent: 6297700 (2001-10-01), Sevic et al.
patent: 6429510 (2002-08-01), Moller
patent: 6583673 (2003-06-01), Ahl et al.
Fujitsu FLL2400IS-2C.
Miller Monte Gene
Staudinger Joseph
Choe Henry
Freescale Semiconductor Inc.
Toler Larson & Abel, LLP
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