Amplifiers – With semiconductor amplifying device – Including gain control means
Reexamination Certificate
1999-03-19
2001-02-13
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including gain control means
C330S307000, C330S310000
Reexamination Certificate
active
06188283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an amplifier used for high-frequency circuits of television sets, communication apparatuses, etc. and capable of changing the gain thereof, and to a semiconductor device wherein the amplifier is integrated on a semiconductor substrate as a semiconductor integrated circuit and sealed in a package. More particularly, the present invention relates to improvement in the amplification efficiency of the amplifier at low gain.
2. Related Art
As amplifiers for high-frequency circuits of television sets, communication apparatuses, etc., semiconductor integrated circuits comprising field-effect transistors and each accommodated in a single package are commonly used. As one of these semiconductor integrated circuits, an amplifier having both gain and output power control functions is available.
FIG. 4
is a circuit diagram showing an amplifier comprising an amplifier having a gain control function (see Japanese Laid-open Patent Application NO. Hei 7-38352) combined with a field-effect transistor at the output stage thereof.
The circuit configuration of
FIG. 4
will be described below in detail. The gate of a signal-amplifying field-effect transistor
1
in a first stage is connected to a amplification signal input terminal
4
via a coupling capacitor (coupling capacitance)
16
. The control output end
19
b
of a gain control circuit
19
is connected to the gate (control portion) of the signal-amplifying field-effect transistor
1
. The control input end
19
a
of the gain control circuit
19
is connected to a gain control terminal
3
. The grounding end
19
c
of the gain control circuit
19
is grounded, i.e., connected to a ground GND used as a reference voltage line. Furthermore, the drain (main electrode; in some cases, the source may function as the main electrode) of the signal-amplifying field-effect transistor
1
is connected to a power voltage application terminal
5
via a drain bias choke coil
7
. Moreover, the source of the signal-amplifying field-effect transistor
1
is grounded, i.e., connected to the ground GND used as the reference voltage line (common connection portion) via a parallel circuit comprising a source voltage self-bias resistor
12
and a capacitor
13
. Additionally, the drain of the signal-amplifying field-effect transistor
1
is connected to the gate of a signal-amplifying field-effect transistor
2
in the next stage (the final stage in this example) via a coupling capacitor
17
. The reference voltage line is not limited to the ground GND.
The gate of the signal-amplifying field-effect transistor
2
is connected to a gate bias voltage application terminal
9
via a gate bias setting resistor
10
and grounded, i.e., connected to the ground GND via a gate bias setting resistor
11
. The drain of the signal-amplifying field-effect transistor
2
is connected to a power voltage application terminal
6
via a drain bias choke coil
8
. In addition, the source of the signal-amplifying field-effect transistor
2
is grounded, i.e., connected to the ground GND via a parallel circuit comprising a source voltage self-bias resistor
14
and a capacitor
15
. Furthermore, the drain of the signal-amplifying field-effect transistor
2
is connected to an amplification signal output terminal
18
.
The signal input portion of the amplifier shown in
FIG. 4
, i.e., the gate of the signal-amplifying field-effect transistor
1
is provided with the attenuation-type gain control circuit
19
wherein part of an input signal is flown to the grounding terminal depending on gain control voltage applied to the gain control terminal
3
. By the attenuation-type gain control circuit
19
, input power to the signal-amplifying field-effect transistor
1
is reduced, whereby the output power of the amplifier can be reduced. When the input to the amplifier is assumed to be constant at this time, the output of the signal-amplifying field-effect transistor
1
changes depending on the gain control voltage (gain control signal) applied to the gain control terminal
3
. As a result, the output of the signal-amplifying field-effect transistor
2
in the next stage, i.e., the output stage wherein the output of the signal-amplifying field-effect transistor
1
is received and amplified further also changes.
FIG. 5
shows the relationship between gain control voltage Vagc applied to the gain control terminal
3
and the output power Pout of the output terminal
18
, and the relationship between the gain control voltage Vagc and the amplification efficiency &eegr; of the amplifier (output power Pout/power consumption P: the power efficiency of the amplifier required for input signal amplification). A solid line a represents the characteristic of the output power Pout at the output terminal
18
with respect to the gain control voltage Vagc. A broken line b represents the amplification efficiency &eegr; of the amplifier with respect to the gain control voltage Vagc. The output power changes depending on the gain control voltage Vagc as shown by the solid line a. This indicates that output voltage control is carried out.
In the above-mentioned conventional amplifier, the gate bias voltage of the signal-amplifying field-effect transistor
2
is set at a fixed value. Therefore, a relatively large drain current (main DC current) flows through the signal-amplifying field-effect transistor
2
even when the output power Pout is low. This causes a problem of lowering the amplification efficiency &eegr; to about 10% or less at low output as shown by the broken line b of FIG.
5
.
For this reason, in portable terminals and apparatuses required to have reduced power consumption in particular, amplification efficiency related to power consumption efficiency is required to be improved. In digital communications in particular, transmission output is frequently required to be controlled depending on the distance from a base station. This case causes a serious problem of reducing amplification efficiency at low output. However, if an amplifier is designed to have high amplification efficiency at low output, a problem of deteriorating a distortion characteristic in signal amplification at high output, and the like are caused. Therefore, the amplifier is forced to be designed so that the characteristics of the amplifier become optimal at high output.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an amplifier capable of raising amplification efficiency at low output while preventing the distortion characteristic thereof from deteriorating at high output.
Another object of the present invention is to provide an amplifier capable of reducing power consumption on the whole at the time when the amplifier is integrated.
The amplifier of the present invention is configured such that a signal-amplifying field-effect transistor having a gain control function in one stage, a signal-amplifying field-effect transistor in the next stage, and the like are connected via a coupling capacitor at least in two stages, wherein the bias voltage control circuit thereof is configured to reduce the drain current of the signal-amplifying field-effect transistor in the latter stage at the time when output power is lowered. With this configuration, amplification efficiency at low output is raised while preventing the distortion characteristic at high output from deteriorating, and a semiconductor device wherein the amplifier is integrated has low power consumption.
The present invention will be described below more specifically.
The amplifier of the present invention comprises signal-amplifying field-effect transistors at least in two stages, a gain control circuit and a bias voltage control circuit.
The above-mentioned signal-amplifying field-effect transistors at least in two stages are connected in cascade from the input side to the output side of an amplification signal so as to have a configuration wherein the main electrode of the signal-amplifying field-effect transistor in the former stage is connected to
Hagio Masahiro
Inamori Masahiko
Motoyoshi Kaname
Tara Katsushi
Matsushita Electric - Industrial Co., Ltd.
Nguyen Patricia T.
Pascal Robert
Stevens Davis Miller & Mosher L.L.P.
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