Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-04-18
2002-08-13
Nguyen, Patricia (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S255000, C330S260000, C330S261000, C330S301000
Reexamination Certificate
active
06433635
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an operational amplifier having large output current, particularly to an amplifier for driving a headphone and an amplifier for driving a speaker utilized for acoustic apparatus and an amplifier suitable for other heavy load drive.
2. Description of the Related Art
In related arts, according to an amplifier for providing large output current, there are provided circuit constitutions as shown by
FIG. 17
, FIG.
18
and FIG.
19
. For convenience, in the drawings, the same constituent elements are designated by the same notations. According to the circuit constitution shown in
FIG. 17
, a power buffer is constituted by connecting the sources of a P-channel MOS transistor Tr
1
the drain of which is connected to a negative power source terminal VSS (for example, 0V) and an N-channel MOS transistor Tr
2
the drain of which is connected to a positive power source terminal VDD (for example, 5V) and providing an output terminal OUT, a resistor RN
1
and a constant voltage circuit VN are connected in series between an output terminal of an operational amplifier (hereinafter, simply referred to as OP amplifier)
1
and the positive power source terminal VDD from the side of the positive power source terminal VDD, a connection point connecting the resistor RN
1
and the constant voltage circuit VN is connected to the gate of the N-channel MOS transistor Tr
2
, a resistor RP
1
and a constant voltage circuit VP are connected in series between the output terminal of the OP amplifier
1
and the negative power source terminal VSS from the side of the negative power source terminal VSS, a connection point for connecting the resistor RP
1
and the constant voltage circuit VP is connected to the gate of the P-channel MOS transistor Tr
1
and although not illustrated, a feedback resistor is connected between the output terminal OUT and a negative phase input terminal VINN. Further, feedback resistors are similarly provided also in the circuit constitutions of FIG.
18
and FIG.
19
. Although not particularly illustrated, the constant voltage circuits VP and VN are publicly-known constant voltage circuits which are arranged proximately to the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
and are constituted by transistors or diodes and resistors thermally coupled thereto. Thereby, temperature-compensated desired idling current is made to flow to the P-channel MOS transistor Tr
1
and the N-channel transistor Tr
2
and an alternating current signal applied to the negative phase input terminal VINN of the OP amplifier
1
, is amplified with small distortion caused by temperature variation. In this case, the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
carry out only current amplification.
FIG. 20
shows a relationship among voltages at respective terminals
11
,
12
and
13
and
FIG. 21
shows drain currents of the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
, that is, idling currents II
1
and II
2
, in idling time at which the input signal of the amplifier of
FIG. 17
is brought into a no signal state. Voltage at the positive power source terminal VDD is designated by notation VDD and the voltage at the negative power source terminal VSS is designated by notation VSS (0V). A positive phase input terminal VINP of the OP amplifier
1
is fixed to potential VDD-(VDD-VSS)/2 at intermediary voltage of voltages of the positive power source terminal VDD and the negative power source terminal VSS and in the idling time, the intermediary potential is applied also to the negative phase input terminal VINN of the OP amplifier
1
and the terminal
11
is provided with the same voltage.
Further, according to an amplifier of
FIG. 18
, a power buffer is constituted by connecting the drains of the P-channel MOS transistor Tr
1
the source of which is connected to the positive power source terminal VDD and the N-channel MOS transistor Tr
2
the source of which is connected to the negative power source terminal VSS and providing the output terminal OUT, a resistor RP
1
and a resistor RP
2
are connected in series between the output terminal of the OP amplifier
1
and the positive power source terminal VDD, a connection point for connecting the resistors is connected to the gate of the P-channel MOS transistor Tr
1
, a resistor RN
1
and a resistor RN
2
are connected in series between the output terminal of the OP amplifier
1
and the negative power source terminal VSS and a connection point for connecting the resistors is connected to the gate of the N-channel MOS transistor Tr
2
. The P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
receive bias voltages produced at the connection points of the resistors and the output signal of the OP amplifier
1
and carry out current amplification and voltage amplification.
FIG. 22
shows a relationship among voltages at respective terminals
21
,
22
and
23
and the power source voltage in idling time of the amplifier of FIG.
18
and
FIG. 23
shows drain currents Id
1
and Id
2
of the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
.
According to an amplifier of
FIG. 19
, in the amplifier of
FIG. 18
, the resistors RP
1
and RN
1
are replaced by constant voltage circuits VP and VN and by the constant voltage circuits VP and VN, idling currents of the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
are determined and by driving the transistors by low impedance, influence of gate capacitance is reduced. That is, according to the amplifier of
FIG. 18
, values of the respective resistors are reduced for constituting low impedance formation in order to maintain drivability of the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
, load on the OP amplifier
1
is increased. According to the amplifier of
FIG. 19
, large output power is provided without increasing the burden on the OP amplifier
1
.
According to the amplifier of
FIG. 17
, maximum amplitude is reduced by an amount of threshold voltages (hereinafter, simply referred to as “Vth”) of the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
. In other words, it is difficult to lower the power source voltage. Describing in reference to
FIG. 20
, in idling time, voltage between the terminal
11
and the terminal
12
coincides with Vth of the N-channel MOS transistor Tr
2
and voltage between the terminal
11
and the terminal
13
coincides with Vth of the P-channel MOS transistor Tr
1
. The maximum amplitude, that is, the range of the output voltage becomes a sum of a voltage value produced by subtracting the voltage
12
from the voltage VDD shown in
FIG. 20 and a
voltage value produced by subtracting the voltage VSS from the voltage
13
. Therefore, when the power source voltage is proximate to the sum of Vth's of the respective transistors, the range of the output voltage is narrowed and amplifying operation becomes impossible at the power source voltage having a value smaller than a voltage value VO at which the voltage VDD intersects with the voltage
12
and the voltage
13
intersects with the voltage VSS.
Further, although connection of the N-channel MOS transistor Tr
2
to the side of the positive power source terminal VDD and connection of the P-channel MOS transistor Tr
1
to the side of the negative power source terminal VSS, can be carried out in the case of a discrete element, the connections are difficult to form on the same substrate in an integrated state. Therefore, temperature compensation by thermal coupling of the constant voltage circuits VP and VN and the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
which has been possible in the case of the discrete element, becomes insufficient For example, a timing of simultaneously making OFF the P-channel MOS transistor Tr
1
and the N-channel MOS transistor Tr
2
is widened by temperature variation and there poses a problem of distortion of the
Jordan and Hamburg LLP
Nguyen Patricia
Nippon Precision Circuits Inc.
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