Miscellaneous active electrical nonlinear devices – circuits – and – External effect – Light
Reexamination Certificate
2000-03-22
2002-08-20
Smith, Matthew (Department: 2825)
Miscellaneous active electrical nonlinear devices, circuits, and
External effect
Light
C327S515000
Reexamination Certificate
active
06437635
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an amplification type solid state imaging device output circuit provided with a source follower circuit.
There has conventionally been proposed an amplification type solid state imaging device whose pixels are each provided with an amplifying function, the device operating to read an amplified signal by means of a scanning circuit. In particular, there has been known an APS (Active Pixel Sensor) type image sensor having a CMOS type pixel construction advantageous to the integration thereof with a peripheral drive circuit and a signal processing circuit. According to this APS type image sensor, there are formed a photoelectric conversion section, an amplifying section, a pixel selecting section and a reset section within one pixel, and normally three to four MOS transistors are used in addition to the photoelectric conversion section constructed of a photodiode (PD).
FIG. 6
shows a circuit diagram of the essential part of an amplification type solid state imaging device in which each pixel is constructed of a PD and three transistors (Mabuchi et al., “A ¼ Inch 330k Pixel VGA CMOS Image Sensor”, ITE Technical Report, IPU97-13, March, 1997).
FIG. 6
shows a photodiode D
1
that serves as a photoelectric conversion section, a MOS transistor Q
11
that serves as an amplifying section, a MOS transistor Q
12
that serves as a reset section, a MOS transistor Q
13
that serves as a pixel selecting section, a pixel selecting clock line
11
, a reset clock line
12
, a vertical signal line
13
and a power line
14
. Signal charges to be accumulated in the photodiode D
1
are electrons, and each of the MOS transistors Q
11
, Q
12
, Q
13
, Q
15
, Q
16
, Q
17
and Q
30
is the n-channel type.
The MOS transistors Q
12
and Q
13
are driven by a first vertical scanning circuit
20
and a second vertical scanning circuit
21
via the pixel selecting clock line
11
and the reset clock line
12
, respectively. The MOS transistor Q
15
that serves as a constant current load is connected to the vertical signal line
13
, and a signal on the vertical signal line
13
is conducted to a horizontal signal line
19
via the fourth MOS transistor Q
16
for amplification use and the MOS transistor Q
17
driven by a horizontal scanning circuit
22
. The MOS transistor Q
30
that serves as a constant current load is connected to the horizontal signal line
19
, and a signal OS is outputted via an amplifier circuit
24
. Fixed potentials V
L1
and V
L2
are applied to a gate of the MOS transistor Q
15
and a gate of the MOS transistor Q
30
, respectively.
In
FIG. 6
, the pixels are all constructed of n-channel type MOS transistors and pn junction diodes, and therefore, the pixels can be formed through the normal CMOS processes. On the other hand, analog circuits such as the amplifier circuit
24
and digital circuits such as the vertical scanning circuits
20
and
21
and the horizontal scanning circuit
22
are generally constructed of CMOS circuits. Therefore, both the pixels and the peripheral circuits can be formed through common processes. This allows the power source to be commonized and practically a power voltage V
D
is used for the pixels and the peripheral circuits.
In order to reduce consumption of power in the amplification type solid state imaging device output circuit having the construction shown in
FIG. 6
, it is effective to lower the power voltage V
D
. According to the source follower circuit constructed of the MOS transistors Q
11
and Q
15
, a photodiode potential is applied as an input v
i
to a gate of the MOS transistor Q
11
, and an output v
o
is obtained on the vertical signal line
13
.
FIG. 7
shows a relation between the input v
i
and the output v
o
of the above amplification type solid state imaging device output circuit. Assuming that the power voltage is V
D
, the gate voltage of the MOS transistor Q
15
is V
L
and a threshold voltage of the MOS transistor Q
15
is V
Tn
, then the MOS transistor Q
15
is required to operate in a saturation region (i.e., in a constant current operation region) in order that the input v
i
and the output v
o
have a linear relation, when the equation:
V
o
>V
L
−V
Tn
(1)
should hold.
In order to secure a sufficient operating margin when the power voltage V
D
is lowered, it is required to sufficiently reduce V
L
−V
Tn
. For example, when the characteric curve changes from A to B as shown in
FIG. 7
, V
L
−V
Tn
increases from V
LA
−V
Tn
to V
LB
−V
Tn
, consequently reducing the operating margin from A′ to B′.
On the other hand, the MOS transistor Q
11
inside the pixel has an ability gm to drive the vertical signal line
13
, given by the following equation:
gm={square root over (2
I
0
&mgr;CW/L
+L )}
(2)
where I
D
represents a drain current, &mgr; represents mobility, C represents gate capacitance per unit area, W/L represents channel width/length of the MOS transistor Q
11
. Assuming that a signal line capacity is C
L
, then a time constant &tgr; in the signal line driving stage is expressed by the following equation:
&tgr;=
C
L
/g
m
(3)
Therefore, if the drain current I
D
is small, then g
m
is reduced. As a result, the time constant &tgr; is increased, as a consequence of which the MOS transistor Q
11
becomes unable to drive the vertical signal line
13
to v
o
within a given time.
The value I
D
of the constant current due to the MOS transistor Q
15
is expressed from the relation of the saturation region by the following equation:
I
D
=(&mgr;
CW/
2
L
)(
V
G
−V
T
)
2
(4)
where V
G
represents a gate voltage and V
T
represents a threshold voltage.
With respect to V
G
−V
T
=V
L
−V
Tn
, the drain current I
D
is shown in FIG.
8
. In this case, the value of V
L
−V
Tn
varies depending on variation in the gate voltage V
L
and the threshold voltage V
Tn
.
As described in
FIG. 7
, it is necessary to set V
L
−V
Tn
smaller in order to widen the operating margin. However, in the case that the width of variation &Dgr;V
Tn
of V
Tn
and the width of variation &Dgr;V
L
of V
L
are constant as shown in
FIG. 8
, there occurs a disadvantage that a ratio &Dgr;I
D
/I
D0
of the variation &Dgr;I
D
of I
D
relative to the center value I
D0
of I
D
increases as V
L
−V
Tn
is set smaller.
As shown in
FIG. 9
, the gate voltage V
L
is generally obtained by dividing the power voltage V
D
by resistors R
21
and R
22
. Therefore, the gate voltage V
L
varies according to variation in the power voltage V
D
. The threshold voltage V
Tn
of the MOS transistor Q
15
cannot normally avoid varying within a specified range during the MOS processes. In particular, V
L
−V
Tn
is suppressed to a reduced value in connection with the equation (1), and therefore, the variation in the threshold voltage V
Tn
strongly influences, as a consequence of which the drain current I
D
largely varies within the range of &Dgr;I
D
shown in FIG.
8
. According to this source follower circuit, it is required to satisfy the equations (2) and (3) even with the minimum drain current I
D
from the point of view of the signal line driving ability, and the current value becomes very great at the maximum drain current I
D
, which is contradictory to the reduction in consumption of power.
In regard to the source follower circuit constructed of the fourth MOS transistor Q
16
and the fifth MOS transistor Q
30
, the same argument can hold assuming that the power voltage is V
D
, the gate voltage of the MOS transistor Q
30
is V
L
and the threshold voltage of the MOS transistor Q
30
is V
Tn
.
As a method for suppressing the variation in the threshold voltage of the MOS transistor located on the load side of the source follower circuit in view of the above reasons, there is proposed the one employing a monitor circuit (the prior art reference of Japanese Patent Laid-Open Publication No. SHO 60-58706) as shown in FIG.
10
. This source follower
Conlin David G.
Daley, Jr. William J.
Dinh Paul
Edwards & Angell LLP
Sharp Kabushiki Kaisha
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