Amorphous TFT process

Details Amorphous TFT process Amorphous TFT process

1999-08-12

2001-11-27

Nelms, David (Department: 2818)

Chemistry: analytical and immunological testing

Geochemical, geological, or geothermal exploration

For petroleum oils or carbonaceous minerals

C438S149000, C257S057000

Reexamination Certificate

active

06323034

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of thin film transistor s with particular reference to structures having low photo (leakage) current as well as low dark (hole) current.
BACKGROUND OF THE INVENTION
Thin film transistors are commonly used in Liquid Crystal Displays (LCDs). In general, liquid crystal displays depend on the overlap of two lines (scan and data lines), each carrying approximately half the voltage needed to activate a single pixel of the LCD. In the active matrix version of an LCD, a thin film transistor (TFT) is placed across each of the intersections of the scan and data lines thereby sharpening the cutoff point and enabling a brighter display to be used. Transistors, in general, are well known to be light sensitive, in common with all semiconductors, so that care must be taken to ensure that light used to illuminate the display does not interfere with the behavior of the TFT. A number of schemes exist for accomplishing this. In particular, the gate electrode of the TFT is located between the light source and the semiconducting channel of the device. This scheme, as currently implemented in the prior art, is not fully effective as we now discuss.
In
FIGS. 1
a
and
1
b
we illustrate two examples of thin film transistors typical of the prior art. Referring first to
FIG. 1
a,
we see a transparent insulating substrate
11
on which a gate electrode
12
, typically of chromium, has been formed. This is covered by layer of gate insulation
4
, typically of silicon nitride or silicon oxide. Layers
14
and
15
represent parts of a single layer of undoped amorphous silicon, the difference between them to be explained shortly. Contact is made to layer
14
/
15
through N+ doped amorphous silicon contacts
8
. Leads to these contacts are in the form of chromium layer
5
which, in turn, has been over coated with source and drain electrodes
6
, with a suitable gap left between them.
Considering first
FIG. 1
a,
with the application of a positive voltage to gate electrode
12
, electrons are attracted to the interface between the amorphous silicon
14
/
15
and the gate insulation layer
4
, thereby forming an enhancement layer (conductive channel) which we have marked as layer
14
. As the voltage at
12
is increased so does the thickness of
14
grow until layer
15
disappears and layer
14
makes contact with N+ contacts
8
and, in principle, the device then switches on.
As can be seen, the width of gate electrode
12
is sufficient so that all light
2
from the display is blocked from reaching layer
14
/
15
. However, it can also be seen that, in this design, layer
14
extends all the way to the vertical portions of chromium layer
5
so that some conduction through the channel (i.e. dark current) will begin at low gate voltages long before the intended switch-on voltage has been reached.
The dark current problem has been effectively eliminated in the design shown in
FIG. 1
b.
Although the amorphous silicon channel
16
/
17
extends all the way to chromium contact layer
5
, the conductive portion
16
is limited to the area directly above gate electrode
13
. However, this has been achieved at the cost of not fully blocking light
2
from reaching the channel so this design is subject to significant photo current.
Thus, TFT designs currently available in the prior art must make a compromise between achieving low dark current or low photo current. The present invention discloses a design in which both can be achieved in the same device. Since part of the present invention is a process for manufacturing this device, it is instructive to first review how devices of the type illustrated in
FIGS. 1
a
and
1
b
are currently manufactured.
Referring now to
FIG. 2
, the prior art process begins with transparent substrate
11
onto whose surface a layer of chromium is deposited and then patterned to form gate electrode
12
(seen in cross-section). This is followed by gate insulation
4
, amorphous silicon layer
15
, and doped amorphous silicon layer
8
.
As shown in
FIG. 3
, a channel pedestal is then fashioned out of layers
8
and
15
. This is followed by the deposition of second level metal layer
41
as shown in
FIG. 4
, the final step being the etching of
41
and
8
down to the level of
15
, to form gap
42
as shown in FIG.
5
.
A routine search of the prior art did not uncover any references that disclose either the structure or the process of the present invention. Several of the references that were found were, however, considered to be of interest. For example, Nishihara (U.S. Pat. No. 5,371,398) describes a typical prior art TFT design but adds a light protecting layer over the far side of the exposed portion of the channel. This prevents light from reaching the channel from either direction.
Yoshida et al. (U.S. Pat. No. 5,416,340) insert an insulating layer between the N+ ohmic contacting layer and the amorphous silicon. This has the effect of covering a short length of the amorphous silicon near the source and drain, without actually touching it. Hole-electron pairs that form as a result of light falling on the main (uncovered ) portions recombine before they reach the source or the drain.
Miyake (U.S. Pat. No. 5,552,630) describes a device that is very close to that of Yoshida et al.
Hirano (U.S. Pat. No. 5,652,159) teaches a process for forming a TFT having a lightly doped drain structure.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a novel structure for a thin film transistor along with a process for its manufacture.
Another object of the invention has been that said structure be insensitive to leakage currents associated with illumination from above as well as exhibiting low hole (dark) current.
These objects have been achieved by means of a process which begins in the normal way with the formation of a gate electrode on a transparent substrate followed by its over coating with layers of gate insulation, undoped amorphous silicon, doped amorphous silicon, and a second layer of chromium. The chromium and amorphous silicon layers are then patterned and etched to form a channel pedestal. In a key feature of the invention the vertical side walls of this pedestal are then given a protective coating of oxide or nitride, forming spacers. This is then followed by the deposition of second level metal which is etched to form source and drain electrodes with a suitable gap between them.


REFERENCES:
patent: 5371398 (1994-12-01), Niashihara
patent: 5416340 (1995-05-01), Yoshida et al.
patent: 5552630 (1996-09-01), Miyaka
patent: 5652159 (1997-07-01), Hirano
patent: 5757028 (1998-05-01), Sasaki et al.

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