Amorphous silicon thin film transistor with a depletion gate

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357 4, 357 2314, H02L 2212, H02L 2978, H02L 2701

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active

050179837

ABSTRACT:
The present invention is a high speed thin film transistor with an accumulation gate and a depletion gate. When a positive voltage is applied to the accumulation gate, the electrons are accumulated in the channel region of the accumulation gate and the transistor is operated at the "on" state. If a negative voltage is applied to the depletion gate, the accumulated electrons are depleted, and the transistor is operated at the "off" state. The on-current of the thin film transistor is the same as that of conventional thin film transistors; however, a smaller off-current of the transistor is obtained.

REFERENCES:
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patent: 4425544 (1984-01-01), Barth
patent: 4532536 (1985-07-01), Hatanaka et al.
IBM Technical Disclosure Bulletin, vol. 32, No. 1 (Jul. 1989) pp. 164-165.
H. C. Tuan et al, "Dual-Gate a-Si:H Thin Film Transistors", IEEE Electron Device Letters, vol. EDL-3 (Dec. 1982) pp. 357-359.
J. G. Fossum et al. "Anomalous Leakage Current in LPCVD Polysilicon MOSFET's" IEEE Transactions on Electron Devices, vol. ED-32 (Sep. 1985) pp. 1878-1884.
T. Kodama et al. "A Self-Alignment Process for Amorphous Silicon Thin Film Transistors", IEEE Electron Device Letters, vol. EDL-3, No. 7, (Jul. 1982) pp. 137-139.
K. Okamoto et al., "MES-FETs Fabricated on Doped a-Si Films", Japanese Journal Applied Physics, vol. 24, (Aug. 1985), No. 8, pp. L632-L634.

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