Patent
1990-06-04
1991-11-12
James, Andrew J.
357 4, H01L 2978, H01L 4500
Patent
active
050652028
ABSTRACT:
An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, as gate wiring itnerconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.
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Tanaka Sakae
Watanabe Yoshiaki
James Andrew J.
Nguyen Viet Q.
Seikosha Co. Ltd.
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