Amorphous silicon thin film transistor array substrate and metho

Details Amorphous silicon thin film transistor array substrate and metho Amorphous silicon thin film transistor array substrate and metho

1989-06-26

1991-07-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437101, 357 237, H01L 21283

Patent

active

050343408

ABSTRACT:
An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, a gate wiring interconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.

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