Patent
1990-06-04
1991-05-21
James, Andrew J.
357 2, 357 4, 357 71, H01L 2978, H01L 4500, H01L 2712, H01L 2348
Patent
active
050179845
ABSTRACT:
An amorphous silicon thin film transistor array substrate has a gate insulating layer and an amorphous silicon layer formed on gate wiring. A pattern of a protective insulating layer having a stepped edge is formed on the amorphous silicon layer. An upper electrode of the same material as the source electrode and the drain electrode are formed on the protective insulating layer to cover the stepped edge of the protective insulating layer. A hold capacitance is formed by connecting the upper electrode to a pixel electrode on the substrate.
REFERENCES:
patent: 4404578 (1983-09-01), Takafaji et al.
patent: 4778258 (1988-10-01), Parks et al.
patent: 4816885 (1989-03-01), Yoshida et al.
patent: 4821092 (1989-04-01), Noguchi
Tanaka Sakae
Watanabe Yoshiaki
James Andrew J.
Meier Stephen D.
Seikosha Co. Ltd.
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