Amorphous silicon memory

Details Amorphous silicon memory Amorphous silicon memory

1994-02-22

1994-11-01

Larkins, William D.

Active solid-state devices (e.g., transistors, solid-state diode

Bulk effect device

Bulk effect switching in amorphous material

437172, 365163, H01L 4500

Patent

active

053609816

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to novel semiconductor devices capable of being set and reset to a plurality of different conductance states.
Most semiconductor devices are used in binary digital systems in which the device is in one of two states (e.g. a high and low resistance) which can be used to represent binary 0 and binary 1. However there is increasing interest in devices which can be in more than two states. Devices which can be set and reset into more than two conductance states (as opposed to the two states of digital devices) are potentially useful in structures known as neural networks which attempt to reproduce some of the arrangements of the human brain.
According to the present invention there is provided an analogue memory device capable of being set and reset into a resistance which is a measure of a voltage applied to it and which comprises layer; metal being one of V, Co, Ni, Pd, Fe or Mn; and convert it into an analogue memory device.
The nature of the first conducting layer is not critical as long as it is possible to grow the required amorphous silicon (a-Si) layer upon it. Examples of suitable materials are Cr or V. Examples of unsuitable materials are gold (which diffuses into the a-Si layer and mercury (which is liquid). The first conducting layer need not extend on the whole area of the amorphous silicon overlying it. Reference to the amorphous silicon layer being above the first conducting layer do not carry any implication about the orientation of the device in use but are intended to indicate only that the silicon is deposited after the first conducting layer.
The amorphous silicon must be dopable i.e. it must be possible to increase its conductivity by incorporating elements having higher or lower valency than silicon. Some techniques of depositing amorphous silicon may give silicon containing high levels of defects which cannot be doped e.g. Argon sputtering of a Si target in the absence silicon are well known to those skilled in the art. Thus low pressure plasma decomposition of silanes (optionally in the presence of hydrogen or fluorine onto a heated substrate may be used).
The deposition of amorphous silicon is discussed in W E Spear and P G LeComber, Topics in Applied Physics, Vol 55, (The Physics of Hydrogenated Amorphous silicon I) 1984 pages 65-71.
The amorphous silicon is doped. The silicon may be doped to produce n-type conductivity by incorporating an element with a higher valency e.g. P, or may be doped to give p-type conductivity as a result of introducing element of lower valency e.g.B.
The amorphous silicon is, preferably, doped so as to have a conductivity in the bulk state of at least 10.sup.-6 (ohms cm).sup.-1. The degree of doping is more preferably such as to correspond to p.sup.+ or n.sup.+ -silicon e.g. to conductivities greater than 10.sup.-4 (ohms cm).sup.-1.
Methods of producing doped amorphous silicon are well known to those skilled in the art. The silicon is preferably p.sup.+ silicon.
The thickness of the doped amorphous silicon is preferably in the range 200 Angstroms to 0.35 micrometers (20 to 350nm). The amorphous silicon layer may be pure hydrogenated amorphous silicon (apart from any doping) or may be a hydrogenated silicon alloy, e.g. a silicon germanium alloy.
The dopable silicon or silicon alloy may contain fluorine.
The identity of the top contact is important in obtaining analogue memory properties. In the production of semiconductor devices semiconductor layers are often deposited on a conducting substrate and a metal layer is deposited in a final step after the semiconductor layers have been deposited. This metal layer is the top contact of the device. The metal layer may, of course, be covered by encapsulating layers or by an additional metal layer which is used to obtain better contact with the metal layer in direct contact with he silicon. It is common in the semiconductor industry to stack devices one above the other in integrated circuits. It may be possible to stack other semiconducting and conducting layers above the device of the

REFERENCES:
patent: 4228524 (1980-10-01), Neale et al.
patent: 4446168 (1984-05-01), Kato et al.
patent: 4665428 (1987-05-01), Hockley et al.
Applied Physics Letters, vol. 40, No. 9, 1 May 1982, New York US, pp. 812-813, den Boer: "Threshold switching in hydrogenated amorphous silicon".

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