Always-deterministic phase-locked loop

Details Always-deterministic phase-locked loop Always-deterministic phase-locked loop

1998-12-16

2000-12-05

Nuton, My-Trang

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

H03L 700

Patent

active

061572330

ABSTRACT:
In some embodiments, the invention includes a system having a normal operating mode and a suspend mode. The system includes event recognition circuitry to provide an event status signal. The system also includes clock generating circuitry with selective stretching capability to generate an internal clock signal and to receive the event status signal, and wherein when the event status signal has a first logic state, the clock generating circuitry stretches the internal clock signal by a number of phases per cycle of a bus clock signal wherein an alignment relationship between the internal clock signal and the bus clock signal is immediately deterministic in transitions between the suspend mode and the normal operating mode.

REFERENCES:
patent: 5630107 (1997-05-01), Carmean et al.
patent: 5634116 (1997-05-01), Singer
patent: 5862373 (1999-01-01), Pathikonda et al.
patent: 5926053 (1999-07-01), McDermott et al.
patent: 5935253 (1999-08-01), Conary et al.
patent: 6021500 (2000-02-01), Wang et al.

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