Television – Synchronization – Sync separation
Reexamination Certificate
2005-12-20
2005-12-20
Miller, John (Department: 2614)
Television
Synchronization
Sync separation
C348S521000, C348S522000
Reexamination Certificate
active
06977692
ABSTRACT:
A circuit for generating video synchronization timing signals includes a negative peak detector (FIG.5) for following variations of a composite video signal (FIG.1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIPrepresentative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700, 702, 704) is used to add an offset VSLICEto VTIP, VSLICEbeing a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments. The sample and hold circuit generates a signal VREF, and is connected by a resistor divider (708,710) to the negative peak detector to form the signal VTIP+VSLICEprovided to an amplifier (606) functioning as a comparator. The signal VSLICE+VTIPis compared in comparator (606) with the composite video signal to provide an overall circuit output. Buffering is provided at the input of the negative peak detector by amplifier (600) to reduce any DC offset from the diode of the negative peak detector. To prevent amplifier DC offset error voltages from affecting the perceived VSLICElevel, an amplifier (800) can be connected in a first position TTIPas part of a negative peak detector to store VTIPon a capacitor, in a second position THas part of a sample and hold circuit to store VREFon a capacitor, and in a third position TCOMPto compare VSLICE+VTIPmeasured from the capacitors with the composite video signal to generate the overall circuit output.
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Elantec Semiconductor, Inc
Fliesler & Meyer LLP
Miller John
Tran Trang U.
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