Alternating polarity carry look ahead adder circuit

Details Alternating polarity carry look ahead adder circuit Alternating polarity carry look ahead adder circuit

1995-04-07

1997-04-08

Ngo, Chuong D.

Boots, shoes, and leggings

G06F 750

Patent

active

056194420

ABSTRACT:
A carry look ahead circuit is implemented such that only one gate delay is incurred in calculating the carry output after the carry input becomes valid. The carry input and the carry output have opposite logical polarities. "Odd" carry look ahead stages are defined to have a positive logic carry input and a negative logic carry output, while "even" stages are defined to have a negative logic carry input and a positive logic carry output. Using "alternating polarity" in this manner simplifies the logic design of both odd and even stages. In a first embodiment, the generate and propagate computations are performed by a separate logic block. As the level of look ahead increases, the complexity of the generate and propagate block increases, but the remainder of the circuitry is unaffected. In a second embodiment, the generate and propagate signal computations are integrated into a complex gate which produces the carry output of each stage. In this manner, a reduction in the number of transistors used and circuit complexity is achieved over the first embodiment. Using more stages with less latency per stage reduces the total hardware required to accomplish a fixed latency. The minimum achievable propagation delay is reduced because the delay from carry input to carry output in each alternating polarity carry look ahead stage is less.

REFERENCES:
patent: 3700875 (1972-10-01), Saenger et al.
patent: 4962471 (1990-10-01), Cornelissen
patent: 5027321 (1991-06-01), Knauer et al.
patent: 5047974 (1991-09-01), Young
patent: 5117386 (1992-05-01), Persoon et al.
patent: 5257218 (1993-10-01), Poon
patent: 5278783 (1994-01-01), Edmondson
patent: 5375081 (1994-12-01), Anderson
patent: 5499203 (1996-03-01), Grundland
Electronics Letters, vol. 28, #5, Feb. 27, 1992, pp. 476-477 J. B. Kuo et al "BiCMOS Dynamic Manchester Carry Look Ahead Circuit for High Speed Arithmetic Unit VLSI".
Alan Y. Kwentus, Hing-Tsun Hung and Alan N. Willson, Jr., "An Architecture for High-Performance/Small-Area Multipliers for Use in Digital Filtering Applications" IEEE Journal of Solid-State Circuits, vol. 29, No. 2, Feb. 1994, pp. 117-121.
N.H.E. Weste and K. Eshraghian, "Principles of CMOS VLSI Design: A Systems Perspective" Addison-Wesley, 1994, pp. 526-536 and 622-623.

Affiliated with

Also associated with

Rating

Alternating polarity carry look ahead adder circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Alternating polarity carry look ahead adder circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Alternating polarity carry look ahead adder circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2401429