Alternate row-based reading and writing for non-volatile memory

Details Alternate row-based reading and writing for non-volatile memory Alternate row-based reading and writing for non-volatile memory

2008-03-25

2008-03-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185010, C365S189011

Reexamination Certificate

active

07349260

ABSTRACT:
A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines.

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Restriction Requirement, United States Patent & Trademark Office, U.S. Appl. No. 11/321,346 filed on Dec. 29, 2005, Oct. 2, 2007.

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