Alternate phase dual compression-tree multiplier

Details Alternate phase dual compression-tree multiplier Alternate phase dual compression-tree multiplier

2006-04-11

2006-04-11

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07028068

ABSTRACT:
A multiplier includes a plurality of subunits. Each of the plurality of subunits is configured to perform a portion of a multiplication operation, and the plurality of subunits are coupled together to perform the multiplication operation. At least a first subunit of the plurality of subunits and a second subunit of the plurality of subunits are configured to perform a same portion of the multiplication operation. The first subunit and the second subunit are clocked at a first clock frequency, during use, that is less than a second clock frequency at which a remainder of the plurality of subunits are clocked during use. The first subunit and the second subunit each have inputs coupled to a third subunit of the plurality of subunits to receive multiplication operations to be operated upon by the respective first subunit and second subunit.

REFERENCES:
patent: 4972362 (1990-11-01), Elkind et al.
patent: 5047973 (1991-09-01), Steiss et al.
patent: 5113364 (1992-05-01), Ho et al.
patent: 5675527 (1997-10-01), Yano
M. J. Flynn, et al., “EE 486 Lecture 8: Integer Multiplication,” Computer Architecture and Arithmetic Group, Stanford University, Feb. 5, 2001, 6 pages.
Gary Bewick, et al., “Binary Multiplication Using Partially Redundant Multiples,” Technical Report No. CSL-TR-92-528, Jun. 1992, pp. 1-21.
Hesham Al-Twaijry, et al., “Performance/Area Tradeoffs in Booth Multipliers,” Technical Report: CSL TR-95-684, Nov. 1995, pp. 1-18.

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