Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-12-21
2003-09-16
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S628000
Reexamination Certificate
active
06622154
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to hardware multipliers, and more specifically to an apparatus and method for producing partial products which may be utilized in hardware multiplication.
BACKGROUND OF THE INVENTION
Many of the processes performed by information handling systems and the like involve the multiplication of binary numbers. In a multiplication function, there exists a multiplicand and a multiplier. Well known to the art, binary numbers are multiplied through a process of multiplying the multiplicand by the first bit of the multiplier. Next, the multiplicand is multiplied by the second bit of the multiplier, shifting the result one digit and adding the products. This process is continued until each bit of the multiplier has been multiplied by the multiplicand.
Each of the products produced by multiplying the multiplicand by a bit of the multiplier produces a number which is referred to as a partial product. The resulting product is formed by accumulating the partial products propagating the carries from the rightmost columns to the left. This process is referred to as partial product accumulation. Although this process works well for its intended purpose, it has a significant drawback in that in order to implement this process utilizing hardware, a significant number of items of hardware are required. As a result, implementing this process with hardware may be cost prohibitive and may be slow especially for large bit numbers.
In order to speed up the process, the Booth algorithm has been utilized. This algorithm allows for a reduction of the number of partial products using a redundant number system. When this process is implemented in hardware, the bits of the multiplier must be separately recoded in order to produce the partial products. Unfortunately, this requires an additional step which slows the process.
Consequently, it would be advantageous to provide an apparatus and method for generating partial products which did not require the additional step of recoding the multiplier bits. By eliminating the recoding of the multiplier bits, the process time is reduced.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a novel apparatus for the generation of partial products for a hardware multiplier. The partial product generator of the present invention does not require recoding of the bits of the multiplier prior to entering the partial product generator of the present invention in order to generate the partial products. The present invention is further directed to a method of producing partial products for a hardware multiplier by directly sending the multiplier bits to the partial product generator of the present invention.
REFERENCES:
patent: 5231415 (1993-07-01), Hagihara
patent: 5677863 (1997-10-01), Naffziger
patent: 5935198 (1999-08-01), Blomgren
patent: 6411979 (2002-06-01), Greenberger
Angarai Vijayanand
Hayashi Naoki
Do Chat C.
LSI Logic Corporation
Ngo Chuong Dinh
Suiter - West PC LLO
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