Alpha blending calculator

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G06F 738

Patent

active

055174370

ABSTRACT:
The alpha blending calculator of the invention executes an alpha blending calculation in accordance with digital data X, Y, and .alpha.. The alpha blending calculator includes multiplexers which select one of X or Y in accordance with bits of the digital data .alpha., respectively, and a calculating section for shifting outputs of the multiplexers by a predetermined number of bits, respectively, and for calculating a sum of the shifted outputs. The calculating section includes first level to Nth level adding portions, and an adder connected to the outputs of the Nth level adding portion for executing a multi-bit addition. Each of the first level to the Nth level adding portions receives a plurality of stages of data, classifies the plurality of stages of data into quotient groups and a remainder group, calculates a sum and a carry for each of the quotient groups, and outputs the sum, the carry, and the stages of data in the remainder group to the next level adding portion. The outputs of the multiplexers are input as the plurality of stages of data to the first level adding portion, and the outputs of the Nth level adding portion consist of a sum and a carry.

REFERENCES:
patent: 4594678 (1986-06-01), Uhlenhoff
patent: 4852037 (1989-07-01), Aoki
patent: 5113363 (1992-05-01), Orsino et al.
patent: 5285403 (1994-02-01), Quisquater et al.
M. Mehta et al., "High-Speed Multiplier Design Using Multi-Input Counter and Compressor Circuits", Proceedings of the 10th IEEE Symposium on Computer Arithmetic, pp. 43-50, (Jun. 26-28, 1991).
K. Lowe et al., "High-Speed GaAsa 4.times.4-Bit Parallel Multiplier Using Super Capacitor FET Logic", Electronics Letters, pp. 425-426, vol. 23, No. 8 (Apr. 1987).
R. White, et al., "Digital Filter Realizations Using a Special-Purpose Stored-Program Computer", IEEE Transactions on Audio and Electroacoustics, pp. 289-294 vol. AU-20, No. 4, (Oct. 1972).

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