Allocation of resources of a pipelined processor by clock phase

Details Allocation of resources of a pipelined processor by clock phase Allocation of resources of a pipelined processor by clock phase

1994-03-31

1995-06-27

Bowler, Alyssa H.

Boots, shoes, and leggings

395550, 364230, 3642314, 3642318, 3642712, 364DIG1, G06F 1300, G06F 938

Patent

active

054288100

ABSTRACT:
A technique of processing pipeline commands in parallel so as to minimize pipeline stalls. This is accomplished in accordance with the invention without need for the complex resource allocation techniques of the prior art by arbitrating access to critical pipeline resources on the phase of the system clock. For example, one control process may access the critical pipeline resource only during an even phase of the system clock, while a second control process may access the critical pipeline resource only during the odd phase of the clock. These processes may run at the same time if the pipelined instructions being executed by each process have no data dependencies since structural hazards are effectively eliminated by time-sharing the data buses on the respective phases of the system clock. The benefits of dynamically scheduled pipelined systems may thus be obtained without the complex scoreboarding and other scheduling algorithms used in the prior art to prevent pipeline hazards.

REFERENCES:
patent: 4354227 (1982-10-01), Hays, Jr. et al.
patent: 4481578 (1984-11-01), Hughes et al.
patent: 4594655 (1986-06-01), Hao et al.
patent: 4695943 (1987-09-01), Keeley et al.
patent: 4789927 (1988-12-01), Hannah
patent: 5060145 (1991-10-01), Scheuneman et al.
Patterson and Hennessy, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, San Mateo, Calif., 1990, pp. 250-349.
A. C. Barkans, "High Speed High Quality Antialiased Vector Generation", Computer Graphics, vol. 24, No. 4, Aug. 1990, pp. 319-326.

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