Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
2005-12-21
2010-06-08
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S225000
Reexamination Certificate
active
07734897
ABSTRACT:
A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process a sequence of operations including at least one memory access operation. The superscalar data processing apparatus comprises a plurality of execution pipelines for executing the operations, and issue logic for allocating each operation to one of the execution pipelines for execution by that execution pipeline. At least two of the execution pipelines are memory access capable pipelines which can execute memory access operations, and each memory access capable pipeline is associated with a subset of the plurality of execution threads. The issue logic is arranged, for each execution thread, to allocate any memory access operations of that execution thread to an associated memory access capable pipeline. Such a system has been found to provide an effective balance between increasing the efficiency of operation of the superscalar data processing apparatus when employing multiple execution threads whilst also alleviating the need for complex hardware to handle hazard detection.
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Alrobaye Idriss N
ARM Limited
Chan Eddie P
Nixon & Vanderhye P.C.
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