Allocation circuit for parallel busses of data processing system

Details Allocation circuit for parallel busses of data processing system Allocation circuit for parallel busses of data processing system

1984-04-24

1988-02-23

Harkcom, Gary V.

Boots, shoes, and leggings

34082551, G06F 1316

Patent

active

047274794

ABSTRACT:
An allocation system for the use of a data processing system where plural user systems of the data processing system gain access to parallel busses of the data processing system in a sequential manner based on a priority determination. The priority determination involves an allocation circuit for each user that includes a logic network comprising four bistable flip-flops, an edge triggered D flip-flop and a monostable flip-flop. The flip-flop elements in conjunction with a generated request signal, bus approval signal, bus busy signal, bus claim signal, selection duration signal, compare signal, enable signal and greater or equal signal and appropriate AND, NAND, OR and inverter elements determine the winner or next user when plural user requests are received while the bus is busy. The use of the edge triggered D flip-flop allows a user subsequent immediate access if such user wants the bus again and no other user has requested the bus. The allocation system otherwise gives priority to all other entered requests before a current user if such current user has again requested the bus.

REFERENCES:
patent: 4096569 (1978-06-01), Barlow
patent: 4121285 (1978-10-01), Chen
patent: 4130864 (1978-12-01), Schlotterer
patent: 4339808 (1982-07-01), North
patent: 4454581 (1984-06-01), Nystrom
patent: 4482948 (1984-11-01), Holden
patent: 4503495 (1985-03-01), Boudreau
patent: 4541043 (1985-09-01), Ballegeer et al.
patent: 4554628 (1985-11-01), Bell
patent: 4611297 (1986-09-01), Dudley et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 3, Aug. 1979, (Blum).

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