Pulse or digital communications – Repeaters – Testing
Patent
1989-01-03
1992-06-09
Safourek, Benedict V.
Pulse or digital communications
Repeaters
Testing
332104, H04L 2720
Patent
active
051214121
ABSTRACT:
A CPFSK quadrature modulator (300) is disclosed utilizing an all-digital implementation. The serial data input signal (20 ) is formatted into parallel overlapping bits using a shift register (202), an up/down counter (206), and an interpolation counter (204) and applied as address lines to in-phase and quadrature-phase memories (208, 210). A multiple of the bit clock is used to address carrier generation ROMs (216, 218). The carrier signal is then modulated by the in-phase and quadrature-phase data signals (212, 214, 222), converted to an analog signal by a D/A converter (250), and low pass filtered (254) to generate the analog output signal (255). A single ROM (440) is utilized to implement all the look-up tables, multipliers, and adder. The all-digital implementation allows for precise control of the modulation index to h.dbd.0.5.+-.0.05 percent over time, temperature, power levels, etc.
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Motorola Inc.
Parmelee Steven G.
Safourek Benedict V.
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