All-digital phase-locked loop

Details All-digital phase-locked loop All-digital phase-locked loop

2007-08-14

2007-08-14

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C327S160000, C375S376000

Reexamination Certificate

active

10907044

ABSTRACT:
An all-digital phase-locked loop (ADPLL) includes: a digital phase frequency detector (PFD) for generating a detection signal by detecting frequency difference and phase difference between a reference signal and a feedback signal; a digital phase difference counter coupled to the digital PFD for sampling the detection signal according to an oscillator signal to thereby generate a count value; a digital filter coupled to the digital phase difference counter for generating a control signal according to the count value; a digital controlled oscillator (DCO) coupled to the digital filter for generating the oscillator signal according to the control signal; and a frequency divider coupled to the DCO and the digital PFD for generating the feedback signal by dividing the oscillator signal.

REFERENCES:
patent: 6275553 (2001-08-01), Esaki
patent: 6404247 (2002-06-01), Wang
patent: 6680633 (2004-01-01), Gailhard et al.
patent: 6965660 (2005-11-01), Strohmayer
patent: 1095248 (2002-11-01), None
Jim Dunning, Gerald Garcia, Jim Lundberg, and Ed Nuckolls, “An all-digital phase -locked loop with 50-cycle lock time suitable for high-performance microprocessors”, pp. 412-pp. 422 IEEE journal of solid-state circuits, vol. 30, No. 4, Apr. 1995.

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