All digital phase-locked loop

Details All digital phase-locked loop All digital phase-locked loop

1995-11-13

2002-06-11

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S105000

Reexamination Certificate

active

06404247

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an all-digital phase-locked loop (PLL). More specifically, the present invention relates to an improved all-digital phase-locked loop, which provides the advantages of lowered cost, high stability, and can be implemented with a very narrow loop bandwidth.
BACKGROUND OF THE INVENTION
A phase-locked loop (PLL) is an electronic circuit for locking an oscillator in phase with an input signal. In other words, a PLL is an electronic circuit for synchronizing, in frequency as well as in phase, an output signal with a reference signal. A PLL can act as a demodulator to demodulate a carrier frequency, or it can be used to track a carrier or synchronizing signal whose frequency varies with respect to time.
PLLs have found a variety of important applications in, for example, communication systems, computers, television engineering, etc. In general, PLLs can be classified, based on its method of implementation, into three main types: analog, mixed digital/analog, and all digital PLLs. A basic analog PLL consists of a phase detector and a low pass filter with a feed back loop closed by a local voltage-controlled oscillator (VCO). The phase detector detects and tracks small differences in phase and frequency between the incoming signal and the VCO signal, and provides output pulses that are proportional to the detected difference. The low-pass filter removes alternating current (ac) components to provide a direct-current (dc) voltage signal to drive the VCO. The input voltage will act to change the output frequency of the VCO to that of the input signal. The phase detector and low-pass filter function as the mixer in a general feedback loop. The output is driven in the direction that will minimize the error signal, such as in frequency. Accordingly, the loop tends to drive the error signal back toward zero frequency. Once the two frequencies are made equal, the output from the VCO will be locked into the input signal, and any phase difference between the two signals will be controlled.
Recently, all-digital PLLs have been developed which provide several advantages over the analog PLLs, including: (1) high yield rate from the IC process; (2) low cost, (3) high stability; (4) can be implemented without external components, such as VCXO, loop filter, etc.; (5) can be implemented with a very narrow loop bandwidth; and (6) can be implemented in a single PLD, thus fostering system development. Some of the most commonly used digital PLLs include SN54LS297 and SN74LS297, both are available from Texas Instrument. The two chips are essentially identical in specification except that the former can operate at a broader temperature range (−55° C. to 125° C.) than the latter (0° C. to 70° C.).
While the all-digital PLLs provide many advantages over their analog counterparts, there is also a very important drawback: they need a substantially higher frequency sample clock than the input clock to divide the input clock period into a fractional of the unit interval (UI). The extent to which the sample clock must be faster than the input clock depends on the maximum permissible output jitter. For an E1-rated output (2.048 M Hz), if the maximum allowable output jitter is to be controlled below 1/32 UI, the conventional all-digital PLL would need a sample clock with a frequency as high as 131.072 M Hz or 65.536 M Hz. The requirement of such a high frequency sample clock can substantially increase the design complexity and the cost thereof.
In an article entitled: “PHDPLL for SONET Desynchronizer”, by Chii-Min Loau and Ji-Tsu Wu, it is disclosed a phase-hopping digital PLL (PHDPLL) for high-speed desynchronization which provided very narrow bandwidth (below 1 Hz). The PHDPLL included the conventional EXclusive-OR (EXOR or XOR) phase detector and a phase-hopping digitally controlled oscillator (PHDCO). The PHDPLL uses the delay time of a basic gate (e.g., a buffer or an OR gate) to cause a phase hopping and thereby a phase step, and does not require a sample clock which is required by a conventional all-digital PLL. However, the gate delay utilized in the PHDPLL is highly susceptible to variations due to fluctuations in the local temperature, process and voltage. The variation in the gate delay can range from as high as twice as much as the designed value to as low as one-half of the designed value. Such a large variation in the intended gate delay can result in failures in attempting to acquire the lock-in, or generate a large output jitter.
Because of the above mentioned shortcomings, there exist needs to design an improved all digital PLLs which can be implemented with a sample clock operating at a substantially lower frequency than that is required in the current system, and exhibit the required stability which will be independent of temperature, process, voltage and other environmental variations.
SUMMARY OF THE INVENTION
The primary object of the present invention is to develop an improved all-digital phase-locked loop. More specifically, the primary object of the present invention is to develop an all-digital phase-locked loop which can be implemented with a sample clock operating at a substantially lower frequency that what would be required by the conventional all-digital phase-locked loops. The all-digital phase-locked loop disclosed in the present invention also exhibits excellent stability which is independent of temperature, process, voltage and other environmental variations such as the initial state. With the improved all-digital PLL disclosed in the present invention, the sample clock can be reduced to ½ or ¼ of that required of a conventional all-digital PLLs, while achieving the same or even improved performance at a reduced manufacturing cost. Another distinctive advantage of the improved all-digital PLL disclosed in the present invention is that, because of its excellent stability, the loop's performance can be emulated in advance. This greatly facilitates the implementation and design of the loop, ensures its performance, and keeps the cost down.
In the all-digital PLL disclosed in the present invention, a delay line, which is structurally similar to a pipe line, is designed to provide a plurality of phase-different clocks. The improved all-digital PLL of the present invention comprises five main components: a divide-by-N counter, a divide-by-M counter, a phase-frequency detector (PFD), a K-counter, and a digital control oscillator (DCO). The divisors N and M must be properly chosen in accordance with the clock frequency and the intended application(s), so as to result in the smallest frequency variation for PFD inputs. The PFD is provided to compare the phase and frequency of the two incoming signals &phgr;
in
and &phgr;
out
. The output signals from the PFD depend not only on the phase error but also on the frequency difference &dgr;
&ohgr;
(which equals to &ohgr;
in
−&ohgr;
out
). The PFD can be constructed from two D-type flip-flops, whose outputs are denoted as “UP” (up) and “DN” (down), respectively. Typically, the outputs of a PFD are initialized at “zero states”. If the two input signals are exactly in phase, the positive edges of these two input signals will occur at the same time. Hence, their effects are canceled against each other, and the output from the PFD will be zero until a different situation is detected. When the two input signals are out of phase, the PFD will detect the phase error, which would range from −2&pgr; to 2&pgr;. The output signals “UP” and “DN” from the PFD are sent to the K-counter for adjusting the frequency of the loop's output. When the total pulse width of the “UP” signals is greater than that of the “DN” signals, the frequency of the loop's output will be reduced (i.e., slowed down). On the other hand, when the total pulse width of the “UP” signals is smaller than that of the “DN” signals, the frequency of the loop's output will be increased (i.e., sped up).
The K-counter operates in cooperation with the DCO to produce a signal which is fed bac

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