All-digital minimal jitter frequency synthesizer incorporating a

Details All-digital minimal jitter frequency synthesizer incorporating a All-digital minimal jitter frequency synthesizer incorporating a

1999-03-26

2000-10-03

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synthesizer

327106, 327107, H04L 2720

Patent

active

061278599

ABSTRACT:
An all-digital frequency synthesizing system that will eliminate spurious frequencies that degrade the overall performance of the generation of a binary waveform. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic reference counter. The periodic reference counter will count a number of periods of a periodic reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output signal will be toggled from logic level to another logic level. A new periodic output signal period can be chosen by selecting a new series of count integers in the count retention table. A count compiler will create the series of count integers retained in the count retention table. The series of count integers will be disbursed in a manner to eliminate spurious frequencies from the periodic output signal.

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patent: 5705945 (1998-01-01), Wee
Best, "Phase-Locked Loops", Theory, Design, and Applications, McGraw Hill, Inc., NY, (1993), pp. 202, 214, 216.

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