Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
1998-12-04
2001-01-30
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C331S025000, C360S051000, C375S376000, C327S159000, C327S160000
Reexamination Certificate
active
06181209
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to CD-ROM (compact-disc read-only memory) drive systems, and more particularly, to an all-digital frequency following system which is constructed entirely based on digital circuit elements for use on a high-performance CD-ROM drive system with an operating frequency of above 40 megahertz (MHz).
2. Description of Related Art
During the operation of a CD-ROM drive system, a decoder is used to receive data from a digital signal processor (DSP) and then store the received data in a memory unit, such as a dynamic random access memory (DRAM) unit. To allow the CD-ROM drive system to operate with high performance, it requires the provision of a reference clock signal of a high frequency that can be stably maintained at the desired level.
In conventional CD-ROM drive systems, the reference clock signal is usually generated by a crystal oscillator whose output frequency or a multiple thereof is used as the clock signal. Conventionally, the multiplication of the output frequency of the crystal oscillator is achieved by using a phase-lock loop (PLL) circuit. In addition, high frequency generators or analog PLL devices can be used to directly obtain the desired high frequency.
One drawback to the use of the above-mentioned analog means to generate the high-frequency reference clock signal, however, is that the circuit will be complex in structure and poor in stability. Since most of modern electronic devices are based on digital circuits, there exists, therefore, a need for an all-digital frequency following system which is constructed entirely based on digital circuit elements and capable of generating an output frequency which can be either an integral or an irrational multiple of an input frequency.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide an all-digital frequency following system which can be implemented with fewer than 500 silicon gates on the integrated circuit thereof.
It is another objective of the present invention to provide an all-digital frequency following system which is constructed entirely based on digital circuit elements.
It is still another objective of the present invention to provide an all-digital frequency following system which is capable of generating an output frequency which can be either an integral or an irrational multiple of an input frequency.
It is yet another objective of the present invention to provide an all-digital frequency following system which can be constructed based on low-frequency transistors.
In accordance with the foregoing and other objectives of the present invention, an all-digital frequency following system is provided. Two preferred embodiments of the invention are disclosed.
In the first preferred embodiment, the frequency following system of the invention is capable of generating an output frequency which is, in particular, an integral multiple of an input frequency. Broadly speaking, the frequency following system of this embodiment includes the following constituent parts:
(a) a frequency counter having a first input end receiving said input frequency as a reset signal which resets said frequency counter at the start of each cycle of the input frequency and a second input end receiving the output frequency of said frequency following system as a feedback to thereby count the number of pulses in the output frequency, said frequency counter holding the output count when the count reaches a preset upper limit;
(b) a digital comparator which latches the output of said frequency counter at the start of each cycle of the input frequency and then compares the latched value with a preset reference value; said digital comparator generating an up trigger signal if the latched value is greater than the reference value, a down trigger signal if the latched value is less than the reference value;
(c) an up/down counter whose count range is set between an upper limit and a bottom limit and whose initial count is set at a predetermined value which is increased by one when the up trigger signal is received from said digital comparator and decreased by one when the down trigger signal is received from said digital comparator; when the count of said up/down counter reaches either the upper limit or the bottom limit, the output of said up/down counter is hold at that limit; and
(d) a digitally-controlled oscillator capable of generating an output signal serving the output frequency whose value is in proportion to the output of said up/down counter.
In said digital comparator, the reference value is set to equal to the ratio of the desired output frequency to the input frequency. The first preferred embodiment allows the frequency following system to generate the desired output frequency which is the reference value multiple of the input frequency.
In the second preferred embodiment, the frequency following system of the invention is capable of generating an output frequency which is, in particular, a non-integral multiple of an input frequency. Broadly speaking, the frequency following system of this embodiment includes the following constituent parts:
(a) a first frequency divider, receiving the input frequency as input, for dividing the input frequency by a first integer number N;
(b) a second frequency divider, receiving the output frequency of said frequency following system as input, for dividing the output frequency of said frequency following system by a second integer number X;
(c) a frequency counter having a first input end receiving the output of said first frequency divider as a reset signal which resets said frequency counter at the start of each cycle of the output of said first frequency divider and a second input end receiving the output of said second frequency divider as a feedback to thereby count the number of pulses in the output of said second frequency divider, said frequency counter holding the output count when the count reaches a preset upper limit;
(d) a digital comparator which latches the output of said frequency counter at the start of each cycle of the output of said first frequency divider and then compares the latched value with a preset reference value K; said digital comparator generating an up trigger signal if the latched value is greater than the reference value, a down trigger signal if the latched value is less than the reference value;
(e) an up/down counter whose count range is set between an upper limit and a bottom limit and whose initial count is set at a predetermined value which is increased by one when the up trigger signal is received from said digital comparator and decreased by one when the down trigger signal is received from said digital comparator; when the count of said up/down counter reaches either the upper limit or the bottom limit, the output of said up/down counter is hold at that limit; and
(f) a digitally-controlled oscillator capable of generating an output signal serving the output frequency whose value is in proportion to the output of said up/down counter.
The irrational multiplier is equal to K·X/N. Suitable values can be selected for N, X, and K that allow the value of K·X/N to be equal to the desired ratio of the resultant output frequency to the input frequency.
REFERENCES:
patent: 4380742 (1983-04-01), Hart
patent: 6115443 (2000-09-01), Wu et al.
Huang Jiawei
J C Patents
Kinkead Arnold
Winbond Electronics Corp.
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