Pulse or digital communications – Receivers – Automatic gain control
Reexamination Certificate
2001-07-26
2003-01-21
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Receivers
Automatic gain control
C455S234100, C455S245100, C330S254000
Reexamination Certificate
active
06510188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to automatic gain control (AGC) circuits, or more specifically, to digital AGC circuits designed to process a plurality of signals including burst signals.
2. Discussion of the Prior Art
In a radio receiver it is necessary to regulate the amplitude of the input signal for varying input signal levels. For instance, if the transmission line is capable of transmitting burst signals, it is possible that a receiver is required to receive a 1 &mgr;V signal at one time (when there is no burst signals in the transmission line), and a 1 V signal, a signal six orders of magnitude higher (if there is a burst signal in the transmission line) at another time. Since both signals should produce the same output level, an adjustment range of more than 110 dB may be required. The problem is made more difficult because most of the amplifier stages in the receiver, and certainly the A/D converter, often have a dynamic range less than the total range of signal strength variations which should be accommodated by the receiver. The prior art solution to this problem is to implement in a receiver a conventional automatic gain control function (AGC) of the input signal that allows the receiver to turn down the gain in various parts of the receiver rather than at a single point.
For instance, the AGC function can be implemented in such a way that for a fairly weak signal, the gain is decreased near the A/D converter end of the receiver, and the maximum gain is retained at the receiver front end and at the intermediate frequency (IF) circuit to maintain the best overall noise figure. On the other hand, for stronger input signals, the gain is decreased prior to the A/D and also at some of the intermediate stages as well to maximize the signal-to-noise ratio (SNR).
More specifically, in a conventional AGC circuit, a quasi-synchronization block receives an intermittently transmitted burst modulated signal (IF input signal) for quasi-synchronization demodulation with orthogonal carrier wave signals which are substantially equal in frequency to the carrier wave frequency to obtain two quadrature channels of analog type. A/D converters convert the two output signals from the quasi-synchronization demodulator into respective digital data series consisting of a plurality of bits. The digital data series obtained by the A/D converters are applied to a multiplier. The output of the multiplier is supplied to a demodulator using a DSP (Digital Signal Processor), and also to square circuits. The received signal level is obtained by squaring the respective outputs of the multiplier. The received signal level of the data series obtained by the squaring circuits are added together in an adder to obtain the received signal power of the outputs of the multiplier. A substracter subtracts an output signal level of the adder from the reference value to be set by the AGC loop. The difference value of the output of the substracter is multiplied by a multiplier with a loop gain constant k which determines the AGC loop gain, and the multiplied result is applied to an integrator. The integrator integrates the output of the multiplier and drives the multiplier. The AGC loop is thus established in order to minimize the output value of the substracter.
In the AGC loop, the AGC response time is determined by the loop gain constant k; the response time becomes shorter with the greater gain constant k and becomes longer with the lesser loop gain constant k.
In the conventional AGC circuit for burst signal, it has been generally necessary to decrease the response time of the loop to cope with the burst signal. However, since decreasing the loop response time is equivalent to increasing the loop band, the received level variation components that are superimposed on the received signal also pass through the loop. Such components are coupled to the received signal in the multiplier, thus deteriorating the signal quality. For this reason, there is a limit imposed on the response time for coping with the burst signal.
This problem is exacerbated in a system that deals with multilevel burst signals, for instance, in a QAM modem that should be capable of processing QAM burst signals without deterioration of the signal quality.
What is needed is a digital AGC circuit with a variable response time constant, that is capable of a high quality demodulation of multilevel burst signals, for instance, QAM burst signals.
SUMMARY OF THE INVENTION
To address the shortcomings of the available art, the present invention provides an all digital AGC circuit that implements an automatic gain control function in the QAM digital systems, including QAM modems, that deals with input burst signals including QAM burst signals having at least two maximums (two peaks).
One aspect of the present invention is directed to an all digital automatic gain control (AGC) system that digitally processes the multilevel input burst signal.
In one embodiment, the AGC system of the present invention comprises: an AGC amplifier, an analog-to-digital (A/D) converter, a frequency down converter, a complex lowpass filter (LPF), a power level detector circuit, a logarithmic comparison circuit (LCC), and an error processing circuit. The AGC amplifier is configured to scale an input signal by a scale factor that depends on the amplitude of the input signal, and configured to generate an analog scaled input signal.
In one embodiment, the (A/D) converter is configured to sample and convert the analog scaled input signal into a digital scaled input signal. The complex LPF is configured to filter out at least one image of the digital scaled input signal due to sampling, is configured to limit noise, and is configured to generate an inphase component I of the digital scaled input signal, and a quadrature component Q of the digital scaled input signal. The power level detector circuit is configured to detect a power level of the digital scaled input signal, wherein the LCC is configured to compare the detected power level of the digital scaled input signal to a predetermined reference signal and configured to generate a digital error signal. The error processing circuit is configured to process the digital error signal and configured to determine the scale factor. Finally, the scale factor is used by AGC amplifier to scale the incoming input signal.
In one embodiment, the error processing circuit further comprises: a coefficient damp multiplier, a digital integrator circuit, and a means for converting the digital error signal into an analog error signal. The coefficient damp multiplier is configured to multiply the digital error signal by at least one damping factor, wherein the digital integrator circuit is configured to digitally control at least one predetermined AGC loop time constant.
In one embodiment, the means for converting the digital error signal into the analog error signal further includes a digital-to-analog (D/A) circuit configured to convert the digital error signal into an analog error signal. In an alternative embodiment, the means for converting the digital error signal into the analog error signal further includes a pulse-width modulator.
In one embodiment, the coefficient damp multiplier further comprises a plurality of shift circuits, wherein each shift circuit is configured to implement at least one bit of the digital error signal.
In one embodiment, the digital integrator circuit further comprises an accumulator circuit, and a digital integrator feedback loop circuit. The accumulator circuit is configured to implement each predetermined AGC loop response time (or AGC loop time constant). The accumulator circuit comprises a clipping circuit configured to damp accumulation of the digital error signal in order to limit an upper signal power limit, and to limit a lower signal power limit. In one embodiment, the clipping circuit further comprises a minimum value hard decision logic circuit, and a maximum value hard decision logic circuit.
Another aspect of the present invention is directed t
Danzer Byron Esten
Isaksen David Bruce
Ghebretinsae Temesghen
Tankhelevich Boris G.
Wideband Computers, Inc.
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