Metal working – Barrier layer or semiconductor device making
Reexamination Certificate
2000-10-04
2004-03-09
Graybill, David E. (Department: 2827)
Metal working
Barrier layer or semiconductor device making
C414S936000, C414S937000, C414S939000, C414S940000, C414S941000
Reexamination Certificate
active
06702865
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an alignment processing mechanism and a semiconductor processing unit with the alignment processing mechanism, which can align a substrate to be processed to a predetermined direction before processing the substrate.
2. Disclosure of the Prior Art
In semiconductor manufacturing steps, processing units for a single substrate, which is adapted to process the single substrate such as a semiconductor wafer, are widely used. For example, a multi-chamber processing unit is known as a processing unit for a single substrate. For example, such a multi-chamber processing unit comprises: a carrier chamber for containing a carrier; an alignment chamber for taking a semiconductor wafer from the carrier contained in the carrier chamber and for conducting an alignment process to the semiconductor wafer; a conveying chamber connected to the alignment chamber via a load-lock chamber; and a plurality of processing chambers arranged around and connected to the conveying chamber. The plurality of processing chambers are adapted to continuously conduct a predetermined film-forming process or a predetermined etching process. Some multi-chamber processing units are adapted to conduct a conveyance of a semiconductor wafer, an alignment thereof and a process thereof, consistently under a reduced pressure at a predetermined vacuum level.
Herein, an alignment process is explained. In the alignment chamber, for example, a semiconductor wafer is taken out from the carrier contained in the carrier chamber via a conveying mechanism under an atmospheric pressure. Then, the semiconductor wafer is conveyed to an alignment mechanism. The alignment mechanism detects an orientation-flat (ori-fla) of the semiconductor wafer by means of a detector such as an optical sensor, and conducts an alignment process to the semiconductor wafer. That is, the alignment mechanism turns the semiconductor wafer to a predetermined direction. After conducted the alignment process, the semiconductor wafer is conveyed from the alignment mechanism to the load-lock chamber via the conveying mechanism. Then, the semiconductor wafer is conveyed from the load-lock chamber to a predetermined corresponding processing chamber via the conveying mechanism arranged in the conveying chamber under a reduced pressure. The semiconductor wafer undergoes a predetermined process in the processing chamber. The processed semiconductor wafer is contained in a carrier, which is adapted to contain processed semiconductor wafers, via the conveying chamber, the load-lock chamber and the alignment chamber.
SUMMARY OF THE INVENTION
However, generally, a speed of the alignment process may be a condition for determining a speed of entire sequential processes for the semiconductor wafer (if a time for which the alignment process is conducted is longer than a time for which the semiconductor wafer is processed). Whichever it may or not, in order to raise a throughput, it is an important point to shorten a waiting time (an idle time) of the alignment process. However, as described above, in the case that after the alignment process for a previous semiconductor wafer has been completed, a next semiconductor wafer is conveyed from the carrier chamber to the alignment mechanism, a time for which the next semiconductor wafer is conveyed from the carrier chamber to the alignment mechanism is an idle time of the alignment mechanism. Thus, there is a problem that the throughput is relatively low.
This invention is intended to solve the above problem effectively. The object of this invention is to provide an alignment processing mechanism, which can be used with greater efficiency in order to achieve such a high speed of an alignment process that a throughput may be raised.
In order to achieve the object, an alignment processing mechanism according to the invention is characterized by comprising: a conveying mechanism for conveying a substrate to be processed, an alignment mechanism for aligning the substrate conveyed by the conveying mechanism to a predetermined direction by causing the substrate to rotate, and a buffer mechanism for relaying the substrate from the conveying mechanism to the alignment mechanism.
According to another feature, the buffer mechanism is adapted to temporarily hold the substrate conveyed by the conveying mechanism and to pass the temporarily holding substrate to the alignment mechanism based on a situation of the alignment mechanism.
According to another feature, an alignment processing mechanism further comprises a second conveying mechanism for conveying the substrate aligned by the alignment mechanism.
According to another feature, the buffer mechanism has at least two holding members for holding the substrate in a vicinity of the alignment mechanism. In the case, preferably, the holding members are integratedly able to move vertically with respect to the alignment mechanism, in order to pass the substrate held thereby to the alignment mechanism. In addition, preferably, each of the holding members is adapted to rotate in such a manner that the holding member goes away from a space in which the substrate may move. In addition, preferably, each of the holding members has: a supporting surface for coming in contact with and supporting the reverse surface of the substrate, and a tapered surface inclined from the supporting surface and formed correspondingly to an outside periphery of the substrate.
According to another feature, an alignment mechanism has a stage for being placed the substrate, and a driving mechanism for causing the stage to rotate in a horizontal plane.
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International Preliminary Examination Report of International Appl. PCT/JP99/01766 in English Dated Nov. 24, 2000.
Narushima Masaki
Ozawa Masahito
Graybill David E.
Smith , Gambrell & Russell, LLP
Tokyo Electron Limited
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