Optics: measuring and testing – By alignment in lateral direction – With light detector
Reexamination Certificate
2001-11-30
2004-10-26
Toatley, Jr., Gregory J. (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
With light detector
C356S401000, C356S603000, C356S604000, C430S022000, C430S030000
Reexamination Certificate
active
06809824
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for alignment of vertically adjoining layers of an integrated circuit structure. More particularly this invention relates to an alignment process using scatterometry measurements of latent images in an upper layer of photoresist and a previously formed structural pattern in a lower layer in test fields on a semiconductor substrate.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the horizontal dimensions of features such as metal lines and the spacing between such features have become smaller and smaller. This, in turn, has lead to an increased need for monitoring of the alignment of the features being formed on one layer of the integrated circuit structure with features already formed in an adjacent underlying layer.
Features such as metal lines, vias, trenches, etc. are usually formed on the integrated circuit structure by photolithography wherein a layer of photosensitive material is formed on the integrated circuit structure and selectively exposed to a pattern of radiation such as visible light through a mask or reticle. The radiation results in a chemical change in the portion of the photoresist exposed to the radiation, thereby forming a latent image of the patterned radiation in the photoresist layer corresponding to a change in solubility between the exposed and unexposed portions of the photoresist layer. The latent image is then developed by baking the photoresist layer followed by contact of the baked and exposed photoresist layer with an etchant or developer resulting in removal of either the exposed or unexposed portion of the photoresist layer, depending upon the type of etchant or developer selected, thereby forming a photoresist mask which can be used to form features such as metal lines.
Accuracy of the formation of features in a particular layer of an integrated circuit structure has been optically monitored using scanning electron microscopy (SEM) on a test wafer, followed by adjustments made to correct errors before proceeding with the run of wafers in which the same pattern of features would be reproduced. More recently scatterometry techniques have been used to monitor defects in a test wafer, wherein radiation is reflected or scattered off targeted features arranged in a diffraction pattern on a test wafer and the degree of alteration or scattering of the diffracted light is detected and compared to known patterns of alteration or scattering of the diffracted light, following which suitable adjustments are made before proceeding with the run of wafers, as in the previous SEM monitoring. In either instance, however, an entire test wafer is expended to accomplish the desired testing of the accuracy of the features. Furthermore, although scatterometry has been used to measure latent (undeveloped) images in a single photoresist layer, conventionally, the latent image is developed (by baking of the resist layer and then contacting it with a wet developer or etchant) prior to optical measurement of the resist mask.
Accurate alignment of the features in a particular layer of the integrated circuit structure with features in an underlying layer is also important and must also be monitored. Such monitoring has also been carried out using overlay technology as well as scatterometry. A pattern of parallel lines in one layer, typically a pattern of parallel lines in a 100 &mgr;m by 100 &mgr;m square, is arranged as alternate lines, i.e., the parallel lines in the first layer are arranged such that the parallel lines in the second layer are seen in the spaces between the parallel lines in the first layer and the accuracy of the spacing of the pattern of lines in the upper level to the underlying pattern of lines is measured. However, this has required the use of a test wafer wherein the latent images on the exposed photoresist mask layer are first baked and developed and then analyzed for alignment with the alignment pattern in the underlying layer, necessitating the use of the entire wafer.
It would, therefore, be desirable if the alignment of features on vertically adjoining layers in an integrated circuit structure could be optically monitored without the expenditure of an entire test wafer, and without requiring the development of latent images already formed in selected fields of an upper layer on the wafer.
SUMMARY OF THE INVENTION
The invention comprises a process for measuring alignment of latent images in selected fields of a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in the same selected fields of a lower layer on the substrate by the steps of:
a) forming a test pattern in selected fields of a first layer on a semiconductor substrate;
b) forming a layer of photoresist over the first layer;
c) forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and
d) measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry.
In a preferred embodiment, the test pattern formed in each of the selected fields in the first layer comprises a pattern of parallel spaced apart lines, and the latent images formed in the portions of the photoresist layer in the selected fields above the test pattern in the first layer also comprises a pattern of parallel spaced part lines, with the two sets of lines interspaced between one another and generally parallel to one another to form a diffraction pattern.
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Bischoff, Joerg, et al., “Light-Diffraction-Based Overlay Measurement”, (Presented at the Metrology, Inspection, and Process Control for Microlithography XV at Santa Clara, CA, Feb. 26-Mar. 1, 2001),Proceedings of SPIE, vol. 4344, 2001, pp. 222-233 (Abstract only).
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Eib Nicholas K.
Pasch Nicholas F.
Yates Colin D.
Lauchman Layla
LSI Logic Corporation
Taylor John P.
Toatley , Jr. Gregory J.
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