Television – Synchronization – Automatic phase or frequency control
Patent
1995-12-19
1998-06-09
Lee, Michael H.
Television
Synchronization
Automatic phase or frequency control
348540, H03L 700
Patent
active
057643016
DESCRIPTION:
BRIEF SUMMARY
The invention concerns the field of television and relates to an alignment process and device for processing video signals on transmission.
It relates more particularly to the aligning, relative to the line synchronization signal, of sampling signals and time signals required for the digitizing and processing of the composite video signal which is carried out in a television system. This digital processing is, for example, a scrambling of the composite video signal for a transmission of the scrambled signal for use in a subscription television system.
Circuits for the digital processing of video signals for transmission, which are professional facilities which demand high stability of the synchronization signals, customarily exploit the falling edge of the pulse for horizontal synchronization of the composite video signal or line sync. The line sync recovery devices of general-public receivers, with the intention of better resistance of the transmitted signal to disturbances, especially noise, carry out an integration of the pulse so as to extract from it a time reference in the synchronization pulse, generally the middle of the pulse. The reference used by the circuits for digital processing on transmission, the falling edge of the line sync, is thus lost on reception.
Good quality reception, when digital processing as mentioned above is carried out on transmission of the video signals, generally requires accuracy to within a dot, i.e. a pixel, of the time signals which clock this processing and are used on transmission and on reception. This is, for example, the case with respect to line cut and rotate coding which consists in randomly generating a cut point with each active video line, the 2 segments thus created then being reversed: the cut point in this case needs to be referenced to within a dot in order for the decoder to be able to reconstruct a quality image on reception.
Now, the use of conventional synchronization or delay circuits does not allow for straightforward and flexible alignment of the line synchronization on transmission with that at reception while still preserving accuracy to within a pixel of the time signals with respect to this new synchronization.
A solution consisting in the use of sync recovery circuits of the receiver type is not satisfactory. Indeed, the jitter in the synchronization signal obtained at the output of these circuits, owing to their very design, which is entirely acceptable for receivers, does not, on transmission, enable the video signals to be processed with sufficient accuracy and results in marring of the information transmitted; this is for example, the problem of phase rotation of the color sub-carrier, due to jitter even below about twenty nanoseconds.
Moreover, because the width of the synchronization pulse can vary from one upstream facility to another, the tolerances are specified by the standards, and the synchronization signal extracted by the reception circuits has a different position with respect to the falling edge of the synchronization pulse depending on the upstream facility employed. The aligning of the sync signal in the transmission circuits has therefore to be specific to each installation, thus raising the cost of bringing it into service and maintaining it owing to this non-interchangeability.
The aim of the invention is to alleviate the aforesaid drawbacks.
Its subject is a process for aligning clock signals and time signals for the processing of video signals on transmission, characterized in that it carries out, via a phase-locked loop controlling a clock frequency, a slaving of a comparison signal to the falling edge of the line synchronization pulse, in that it decodes at the output of a counter integrated into the loop and controlled by the clock, on the one hand, a value N triggering the comparison signal and corresponding to a specified position inside the line synchronization pulse relative to its falling edge, and on the other hand, values triggering the rezeroing of the counter and time signals synchronous with the clock and
REFERENCES:
patent: 4688094 (1987-08-01), Tanabe et al.
patent: 5528307 (1996-06-01), Owada et al.
patent: 5600379 (1997-02-01), Wagner
"Thomson-CSF"
Lee Michael H.
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