Alignment pattern for a semiconductor device manufacturing...

Details Alignment pattern for a semiconductor device manufacturing... Alignment pattern for a semiconductor device manufacturing...

2005-07-12

2005-07-12

Williams, Alexander Oscar (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S522000, C257S758000, C257S760000, C257S773000

Reexamination Certificate

active

06917115

ABSTRACT:
An alignment pattern comprises at least a sloped surface which communicates between a top surface of an inter-layer insulator extending over a surface of a substrate and a field oxide film selectively formed over the surface of the substrate and a flat surface of a metal plug, and the flat surface being lower in level than the top surface of the inter-layer insulator. The metal plug is buried within an alignment hole which completely penetrates the insulation layer and at least reaches the field oxide film, so that the alignment hole has a bottom level which is deeper than a bottom level of the inter-layer insulator.

REFERENCES:
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patent: 5770484 (1998-06-01), Kleinhenz
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patent: A 2000-174022 (2000-06-01), None

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