Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1999-09-13
2001-09-11
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S401000, C438S462000, C438S975000
Reexamination Certificate
active
06288453
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to methods for processing semiconductor materials, and in particular to methods for measuring the amount of alignment offset problems in the fabrication of a semiconductor which exist between an interconnect layer and a layer having openings therein such as vias or the like, and provides for effective and efficient electrical and visual alignment confirmation of the location of the openings.
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coat, etching, and deposition. In many of these steps, material is overlaid or removed from the existing layer at specific locations in order to form the desired elements of the integrated circuit. Proper alignment of the various process layers is therefore critical. The shrinking dimensions of modem integrated circuits require increasingly stringent overlay alignment accuracy. If the proper alignment tolerance is not achieved, a device can result which is defective or has reliability problems.
More specifically, semiconductor processes such as described above employ fabrication steps in which aligned openings are formed in contact layers to complete an electrical connection. The interconnect layer is typically a metal layer and the contact layer or via layer is typically an insulating/dielectric layer.
There is thus a need that exists for reducing alignment offset problems between an interconnect layer and the layer containing the openings.
SUMMARY OF THE INVENTION
The above-described needs have been met by the system and method of the present invention which enables the effective and efficient determination of the above-described misalignment between the via and interconnect layers. In this way, defective semiconductors produced in semiconductor wafer fabrication can be readily identified and segregated for shipment to customers.
A single multifunctional structure formed in the interconnect layer can be used to determine the alignment accuracy of contact at via inline visual inspection and end of line electrical examination of the resistance properties of the semiconductor wafer.
Preferably, the unitary multifunctional alignment structure is an integral continuous structural member having a stairstep design for use in maximizing the overlay capabilities with respect to the openings by the unitary multifunctional alignment structure. Furthermore, the integral continuous structural member can include an alignment indicator section comprising a series of individual rectangular stairstep sections which are joined together and offset with respect to each other. The size and relative offset location of the individual rectangular stairstep sections is preferably an inline visual alignment standard for checking the size and relative position of the openings against the design rule of the semiconductor wafer. In one form of this invention, the step of electrically measuring the amount of misalignment of the openings with respect to the multifunctional alignment structure is conducted at the conclusion of the semiconductor wafer formation process.
The present invention can further include the steps of connecting the first interconnect layer to a first bond pad, connecting the second interconnect layer to a second bond pad, and thereby forming an electrical connection between first and second interconnect layers through each of the openings, respectively. Next, an electrical voltage is applied between first and second interconnect layers through each of the openings, respectively. The current between the first and second interconnect layers through each of the openings is measured. In this way, the resistance between the first and second interconnect layers and each of the openings can be calculated, and the alignment accuracy of each of the semiconductor wafers being tested can be electrically measuring based on difference in the resistance between the first and second interconnect layers through each of the openings.
Such a multifunctional alignment structure comprises means for visually comparing the relative position of the openings inline with respect to the multifunctional alignment structure to determine the degree of offset of the openings with the design rule of the semiconductor wafer, and means for electrically measuring the amount of misalignment of the openings with respect to the multifunctional alignment structure to determine the degree of offset of the openings with the design rule of the semiconductor wafer.
The unitary multifunctional alignment structure preferably comprises an integral continuous structural member including an alignment indicator section comprising a series of individual rectangular stairstep sections which are joined together and offset with respect to each other, the size and relative offset location of individual rectangular stairstep sections is an inline visual alignment standard for checking the size and relative position of the openings against the design rule of the semiconductor wafer.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment which proceeds with reference to the drawings.
REFERENCES:
patent: 3808527 (1974-04-01), Thomas
patent: 4386459 (1983-06-01), Boulin
patent: 5861679 (1999-01-01), Nagano
patent: 5898228 (1999-04-01), Sugasawara
patent: 6072192 (2000-06-01), Fulford, Jr. et al.
Lee Eddie
LSI Logic Corporation
Wilson Allan R.
LandOfFree
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