Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2007-05-29
2007-05-29
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S401000, C438S462000, C438S692000, C257S797000, C257SE21546, C257SE21665, C257SE23179
Reexamination Certificate
active
10899253
ABSTRACT:
A scheme for aligning opaque material layers of a semiconductor device. Alignment marks are formed in a via level of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may have about the same length as vias formed in the via layer. The alignment marks comprise trenches that are not filled with material and are not exposed to a CMP process. An opaque material layer is deposited, and depressions are formed in the opaque material layer over the alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.
REFERENCES:
patent: 4592132 (1986-06-01), Lee et al.
patent: 4657629 (1987-04-01), Bigelow
patent: 5002902 (1991-03-01), Watanabe
patent: 5492607 (1996-02-01), Yap
patent: 5503962 (1996-04-01), Caldwell
patent: 5663099 (1997-09-01), Okabe et al.
patent: 5738961 (1998-04-01), Chen
patent: 5786260 (1998-07-01), Jang et al.
patent: 5935764 (1999-08-01), Kakehashi
patent: 5958800 (1999-09-01), Yu et al.
patent: 6010945 (2000-01-01), Wu
patent: 6043133 (2000-03-01), Jang et al.
patent: 6133111 (2000-10-01), Sur et al.
patent: 6146969 (2000-11-01), Tan et al.
patent: 6174737 (2001-01-01), Durlam et al.
patent: 6183614 (2001-02-01), Fu
patent: 6284551 (2001-09-01), Cho et al.
patent: 6319767 (2001-11-01), Cha et al.
patent: 6346454 (2002-02-01), Sung et al.
patent: 6420261 (2002-07-01), Kudo
patent: 6447634 (2002-09-01), Zahorik et al.
patent: 6555925 (2003-04-01), Higashi et al.
patent: 6566157 (2003-05-01), Ohtaka
patent: 6774452 (2004-08-01), Ramkumar et al.
patent: 6780775 (2004-08-01), Ning
patent: 6858441 (2005-02-01), Nuetzel et al.
patent: 6979526 (2005-12-01), Ning
patent: 2001/0001077 (2001-05-01), Tan et al.
patent: 2001/0040778 (2001-11-01), Abraham et al.
patent: 2002/0009876 (2002-01-01), Wege et al.
patent: 2002/0096775 (2002-07-01), Ning
patent: 2002/0098705 (2002-07-01), Low
patent: 2002/0098707 (2002-07-01), Ning
patent: 2002/0100978 (2002-08-01), Tomita et al.
patent: 2002/0153551 (2002-10-01), Wong et al.
patent: 2003/0017707 (2003-01-01), Yamashita et al.
patent: 2003/0224260 (2003-12-01), Ning
patent: 2004/0043579 (2004-03-01), Nuetzel et al.
patent: 2004/0102014 (2004-05-01), Ning et al.
patent: 2005/0079683 (2005-04-01), Sarma et al.
patent: 2006/0141737 (2006-06-01), Gaidis
patent: 102 27 211 A 1 (2003-02-01), None
Bajaj, R., et al., “Manufacturability Considerations and Approaches for Development of a Copper CMP Process,” 1999 VMIC Conference, pp. 144-151, 1999 IMIC 109/99/0144 (c).
Raghavan, S., et al., “Electrochemical Behavior of Copper and Tantalum in Silica Slurries Containing Hydroxylamine,” 1999 VMIC Conference, pp. 619-626, 1999 IMIC 109/99/0619 (c).
Wang, C.T., et al., “Pad Wear Analysis in CMP,” 1999 VMIC Conference, pp. 267-269, 1999 VMIC 109/99/0267 (c).
Wong, K.K.H., et al., “Metallization by Plating for High-Performance Multichip Modules,” IBM J. Res. Develop., Sep. 1998, pp. 587-596, vol. 42, No. 5.
Anya Igwe U.
Baumeister B. William
Infineon - Technologies AG
Slater & Matsil L.L.P.
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