Alignment of local transmit clock to synchronous data...

Details Alignment of local transmit clock to synchronous data... Alignment of local transmit clock to synchronous data...

2007-08-14

2007-08-14

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S146000, C327S151000

Reexamination Certificate

active

11033755

ABSTRACT:
A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for outputting the local clock signal as a phase-adjusted local clock having a selected phase based on a phase selection value specified by the counter. The synchronizer is configured for digitally sampling the received reference clock relative to the phase-adjusted local clock, and outputting a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock. The counter selectively increments or decrements a counted value based on the digital phase bit, and outputs to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value.

REFERENCES:
patent: 4637018 (1987-01-01), Flora et al.
patent: 6182236 (2001-01-01), Culley et al.
patent: 6249189 (2001-06-01), Wu et al.
patent: 6861867 (2005-03-01), West et al.
patent: 6861886 (2005-03-01), Ludden et al.
patent: 2006/0062341 (2006-03-01), Edmondson et al.
“AMD-3181™ HyperTransport™ PCI-X® Tunnel Data Sheet”, 24637 Rev. 3.02, Aug. 10, 2004, pp. 1-87.

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