Alignment of clock domains in packet networks

Details Alignment of clock domains in packet networks Alignment of clock domains in packet networks

2008-01-01

2008-01-01

Chan, Wing (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S509000, C375S356000, C713S375000

Reexamination Certificate

active

10781164

ABSTRACT:
Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points. These steps are continually repeated on new sets of data points created from newly received synchronization packets using the current delay estimate for the expected delay. And a clock domain at the destination is continually aligned with a clock domain at the source based on the current delay estimate for packets traversing the network between the source and destination.

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