Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1998-05-04
2001-05-08
Lee, Eddie C. (Department: 2815)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S975000, C438S946000, C438S401000, C438S462000, C257S797000
Reexamination Certificate
active
06228743
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductors, and more particularly to aligning a semiconductor die on a semiconductor wafer.
Semiconductor devices typically are fabricated as an array of dice formed on a semiconductor wafer. The devices are built up in successive layers of material formed into predetermined patterns. Patterns typically are produced by coating the wafer with a photoresist and activating a light path directed through a reticle functioning as a photomask. An alignment tool is used to align the wafer and reticle by locating an alignment mark on the reticle and one formed on the wafer during a previous processing step. Such alignment marks occupy regions of the wafer surface and can add significantly to the size of a semiconductor die. To minimize the increase in die size, many systems place alignment marks in inactive regions of the die such as scribe grids where there is no active circuitry.
Modern alignment tools electronically align a photomask to a wafer by locating alignment marks with optical sensors. The wafer and photomask positions are determined from the alignment marks and are adjusted by controlling the position of a wafer stage with a stepper motor and a feedback signal. Prior art alignment tools use multiple sets of alignment marks to improve sensing and alignment resolution. The multiple sets of alignment marks improve alignment but occupy a large die area that increases the cost of a semiconductor device.
Hence, there is a need for a semiconductor device aligned with a system that can reduce the die area and resulting manufacturing cost of the semiconductor device.
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Chen Gong
Colclasure Robert D.
Hightower Robert F.
Lee Eddie C.
Motorola Inc.
Richards N. Drew
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