Alignment marks of semiconductor substrate and manufacturing met

Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks

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Details

257308, 438254, 438401, H01L 23544

Patent

active

061407119

ABSTRACT:
An alignment mark which is employed for the alignment of a semiconductor substrate during a lithography process in the production of a semiconductor element, includes a trough-like pattern having a width roughly equal to the width of a circuit element provided at the surface of the semiconductor substrate. Since the width of the trough-like pattern is set roughly equal to that of the circuit element, a secure trough-like pattern that will not be removed to an excessive degree during processes such as etch-back is formed at the surface of the semiconductor substrate, even if the alignment mark is formed concurrently with the formation of the circuit element. Consequently, a clear alignment mark that can be produced concurrently with the formation of a circuit element of the semiconductor circuit element and that presents no risk of collapsing or separating, is provided.

REFERENCES:
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patent: 5811331 (1998-09-01), Ying et al.
patent: 5856220 (1999-01-01), Wang et al.
patent: 5869383 (1999-02-01), Chien et al.
patent: 5877064 (1999-03-01), Chang et al.
patent: 5889335 (1999-04-01), Kuroi et al.
patent: 5915189 (1999-06-01), Sim

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