Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2000-07-27
2004-09-07
Thomas, T. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S401000, C438S462000, C438S975000
Reexamination Certificate
active
06787930
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to an active matrix type liquid crystal display employing an inverted staggered, type thin-film transistor (hereinafter referred to as “TFT”) as an active element and having a color layer on a wafer side where the TFT is mounted, and, in particular, relates to alignment marks which serve as an alignment reference in each production step and a manufacturing method or the same.
2. Description of the Related Art
FIGS. 1A and 1B
show a first embodiment of the prior art, that is, schematic views of a channel etch type TFT of an active matrix wafer in a liquid crystal display.
FIG. 1A
shows a plan view of one picture element,
FIG. 1B
shows a section of a region of the TFT along the cut line I—I of
FIG. 1A
, and
FIGS. 2A and 2B
show sections of a terminal portion. In
FIG. 1B
, a gate electrode
42
a
is formed on a transparent insulated wafer
41
and thereon, a gate insulating film
43
is formed to cover them. Further thereon, a semiconductor layer
44
is formed so as to overlap the gate electrode
42
a
, and a source electrode
46
a
and drain electrode
47
distant on the central part of the semiconductor layer is connected to the semiconductor layer
44
via an ohmic contact layer
45
. The ohmic contact layer between the source electrode
46
a
and drain electrode
47
is removed by etching and the ohmic contact layer
45
is formed only between the source electrode
46
a
, the drain electrode
47
and semiconductor layer
44
. Further, a passivation film
48
is formed so as to cover them. On the passivation film
48
, a transparent conductive film to be a picture element electrode
49
is connected to the drain electrode
47
via a contact through hole
51
penetrating through the passivation film
48
. A switching signal is inputted to the TFT through a gate wiring
42
b
and the source electrode
42
a
, and an image signal is inputted through a source wiring
46
b
and the source electrode
46
a
, whereby a picture element electrode
49
is charged.
Then, a manufacturing method for the active matrix wafer shown in
FIGS. 1A
,
1
B,
2
A and
2
B is explained with reference to
FIGS. 3A
to
3
C and
4
A and
4
B. Here, the TFT portion is shown on the left side of
FIGS. 3A
to
3
C and an alignment portion, which is used for alignment with a mask in an exposure device in each photolithography step, is shown on the right side of
FIGS. 3A
to
3
C. The alignment portion is provided, as shown in
FIG. 5A
, on the outside of a picture element display area
65
of the active matrix wafer.
FIG. 5B
is an enlarged plan view of the alignment portion and
FIG. 5C
is a section thereof.
As shown in
FIG. 3A
, on the transparent insulated wafer
41
made of glass, etc., a conductive layer made from Al, Mo, and Cr, etc. is deposited to be 100 to 400 nm in thickness by sputtering and a first patterning step is performed such that, through a photolithography step, gate wiring (not illustrated), gate lectrodes
2
a
, and gate terminals (tot illustrated) connected to an external signal processing wafer for display are formed. Here, gate alignment marks
63
a
used for overlapping with gate wiring and gate electrodes in the following step are formed outside the display area by the same layer. Then, as shown in
FIG. 3B
, a second patterning step is performed such that a gate insulating film
43
made of a silicon nitride film, etc. and a semiconductor layer
44
made or amorphous silicons and an ohmic contact layer
45
made of n+ amorphous silicon are laminated to be approximately 400 nm, 300 nm, and 50 nm in thickness in sequence, respectively, and the semiconductor layer
44
and ohmic contact layer
45
are collectively patterned. Herein, for patterning, as shown in
FIG. 3B
, alignment between a mask
61
and an active matrix wafer
50
c
is necessary in the exposure device.
The alignment is performed, as shown in
FIG. 3B
, as follows; gate alignment marks
63
a
, formed in the first patterning step where the gate electrode
42
a
, etc. is formed, are used which are aligned with mask side alignment marks
62
formed on a mask
61
. For aligning the alignment marks, as shown in
FIG. 6A
, respective alignment marks formed on the active matrix wafer
50
c
and mask
61
are read by means of a laser beam, whereby the mask side alignment marks
62
and the active matrix wafer side alignment marks
63
are aligned. At this time, for reading the alignment marks, as shown in
FIG. 6B
, an exposure alignment laser
66
is irradiated on alignment marks
60
through a transparent file
67
and a light reflected from alignment marks
60
or, as shown in
FIG. 6C
, a light diffracted from the step portion due to the alignment marks
60
are read. When reading is performed by means of the reflected light, it is necessary that the alignment marks are formed of a metal which reflects the laser beam and if the marks have a film thereon, its material does not absorb the reflected light. Also, when reading is performed by means of the diffracted light based on the step portion, the alignment marks have no restriction in material and if the marks have a film thereon, as shown in
FIG. 6C
, it may be a non-transparent film
68
, an further, it is necessary that the step portion of the alignment marks are not flattened due to the film material and film thickness.
Then, a third patterning step is performed, as shown in
FIG. 3
c
, in that Mo and Cr, etc. are deposit to be 100 to 200 nm in thickness so as to cover the gate insulating film
43
and ohmic contact layer
45
by sputtering and, thereon, source electrodes
46
a
, source wiring
46
b
, drain electrodes
47
, and lower electrodes
47
d
(
FIG. 2B
) of data terminals
47
a
connected to an external signal processing wafer for display are formed by a photolithography step, as shown in FIG.
4
A. Here, in an exposure step, the mask
61
and active matrix wafer
50
c
are aligned, as shown in
FIG. 3C
, by means of the gate alignment marks
63
a
formed in the first patterning stop. Further, as shown in
FIG. 4A
, drain layer alignment marks
63
b
are formed of a drain metal material at the same time in the third patterning step. After the third patterning step, the unnecessary ohmic contact layer
45
on the area other than under the source electrode
46
a
and drain electrode
47
, which serves as a channel portion of the TFT, is removed.
Thereafter, a fourth patterning step is performed, as shown in
FIG. 4A
, in that, a passivation film
48
made of an inorganic film such as a silicon nitride film is formed to be 100 to 200 nm in thickness by the plasma CVD method so as to cover the back channel of the TFT, that is, the source electrode
46
a
, source wiring
46
b
, the drain electrode
47
, and a lower electrode
47
d
of a data terminal
47
a
, a contact through hole
51
for making a contact with the drain electrode
47
and picture element electrode
49
is formed, and unnecessary gate insulating film
43
on the lower electrode
47
d
(
FIG. 2B
) of the data terminal
47
a
and unnecessary gate insulating film
43
and passivation film
48
on the lower electrode (
FIG. 2A
) of the gate terminal
42
c
are removed. Herein, alignment between the mask
61
and active matrix wafer
50
c
in an exposure step is performed, as shown in
FIG. 4A
, by means of the drain layer alignment marks
63
b
formed in the third patterning step.
Lastly, as shown in
FIG. 4B
, a fifth patterning step is performed such that a transparent conductive film
149
to be a picture element electrode is formed by sputtering. Herein, alignment between the mask
61
and active matrix wafer
50
c
in an exposure step is performed, as shown in
FIG. 4B
, by means of the drain layer alignment marks
63
b
formed in the third patterning step.
An active matrix wafer shown in
FIG. 1B
is produced by such a manufacturing method through five patterning steps, and therefore, the production process is significantly shortened. The active matrix wafer is used and combined
Kikkawa Hironori
Maruyama Muneo
Nakata Shinichi
Okamoto Mamoru
Sakamoto Michiaki
Hayes & Soloway P.C.
Lee Eugene
NEC LCD Technologies Ltd.
Thomas T.
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