Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2000-11-30
2002-03-05
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C257S797000
Reexamination Certificate
active
06352904
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of generating alignment marks only on the oxide layers in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, multiple layers of conductors and insulators are deposited and patterned to construct the integrated circuit. It is critical to align each subsequent layer with the previous layer with precision. This is typically accomplished by using alignment marks. A wafer stepper tool uses the alignment marks on a wafer as a reference point for adjusting a reticle over the wafer. The reticle contains the pattern to be generated within the layer. The reticle must be precisely aligned to the previous layer. A wafer stepper uses one of at least three methods to detect the alignment marks; these are light interference, bright field contrast, or dark field polarization effect.
Some methods generate alignment marks within the scribe line area. Scribe lines define a cutting portion where devices formed on a wafer are cut apart after manufacture. Some alignment mark schemes require fresh alignment marks to be generated at every layer, using the previous layer's marks to assure alignment. Alignment marks occupy more and more space as the number of interconnect layers increases and scribe line area becomes scarce. Some alignment schemes transfer the alignment marks from layer to layer. However, this cannot be done when planarization is performed, such as chemical mechanical polishing (CMP). In this case, the alignment marks must be recovered after CMP. These recovery or repair steps lengthen the process cycle and increase the production costs.
U.S. Pat. No. 5,503,962 to Caldwell discloses an alignment mark and CMP process in which alignment marks are formed in oxide layers using the same process as for contact and via formation. However, there is no mention of how to generate a quality alignment mark or of how to use the alignment mark beyond the next layer. U.S. Pat. No. 5,663,099 to Okabe et al teaches a method of forming an alignment mark. U.S. Pat. No. 5,401,691 to Caldwell teaches a method of recovering alignment marks after CMP. U.S. Pat. No. 5,496,777 to Moriyama teaches forming an alignment mark for each layer in a widened portion of a scribe line. U.S. Pat. No. 5,648,854 to McCoy et al discloses an alignment system to detect the wafer edge and global alignment marks.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of generating alignment marks in the manufacture of an integrated circuit device.
A further object of the invention is to provide a method of generating alignment marks in which alignment mark recovery is avoided.
Yet another object is to provide a method of generating alignment marks in which alignment marks are generated only at oxide layers.
A still further object is to provide a method of generating alignment marks in which alignment marks printed on the oxide layer are used for the next two subsequent layers.
Yet another object is to provide a method of generating alignment marks on the scribe lines in which alignment marks are generated only at oxide layers.
Yet another object of the invention is to provide a method of generating alignment marks on the scribe lines in which alignment marks printed on the oxide layer are used for the next two subsequent layers.
In accordance with the objects of this invention a method for generating alignment marks on the scribe lines in which alignment marks are generated only at oxide layers is achieved. An alignment mark is formed in an oxide layer on a scribe line of a wafer. The alignment mark is lined with a metal layer and filled with a dielectric layer which is planarized. The alignment mark is used in aligning a reticle to pattern the metal layer and is also used in aligning a reticle to pattern the dielectric layer wherein the step of lining the alignment mark with the metal layer protects the alignment mark.
REFERENCES:
patent: 5401691 (1995-03-01), Caldwell
patent: 5496777 (1996-03-01), Moriyama
patent: 5503962 (1996-04-01), Caldwell
patent: 5648854 (1997-07-01), McCoy et al.
patent: 5663099 (1997-09-01), Okabe et al.
Chi-Min Yuan et al., Physically-Based Models of Alignment Schemes in Commercial Steppers. 1990 IEEE, pp. 36.2.1-36.2.4.*
John Golz et al., Optical Flatness and Alignment Mark Contrast in Highly Planar Technologies. 1997 IEEE, pp. 300-304.*
Hong JongKyun et al. Effect of CMP Proces on Alignment Accuracy. 1999 IEEE, pp. 494-496.
Neoh Soon Ee
Tan Juan Boon
Chartered Semiconductor Manufacturing Ltd.
Chaudhuri Olik
Duy Mai Anh
Pike Rosemary L. S.
Saile George O.
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