Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2001-02-20
2002-12-24
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S462000, C438S401000
Reexamination Certificate
active
06498401
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to alignment marks and more particularly, to an alignment mark set comprising alignment marks that are formed in an exposure area and used to measure the alignment or overlay accuracy of patterns in the lithographic process for semiconductor device fabrication, and a method of measuring alignment accuracy of patterns using alignment mark sets.
2. Description of the Related Art
Generally, semiconductor devices comprise a lot of layers that form electronic elements, wiring lines, contacts, and so forth, which are stacked to each other along with interlayer dielectric layers. These stacked layers constitute an integrated circuit. Thus, to fabricate semiconductor devices, the stacked layers need to be patterned to form desired electronic elements, wiring lines, and so forth using well-known lithography and etching techniques.
With the lithography and etching techniques, it is very important not only to transfer a desired minute pattern to a specific layer on or over a semiconductor wafer as closely as possible but also to overlay an upper pattern to a lower one as correctly as possible. Thus, in the lithography process, the pattern of a resist layer, which is formed on a layer to be etched or patterned (i.e., a target layer), needs to be aligned on a desired lower pattern located below the target layer with high accuracy. In particular, circuits and elements provided in a recent semiconductor device have been increasingly miniaturized and therefore, the need to raise the overlay accuracy (i.e., alignment accuracy) of patterns has been becoming stronger.
Conventionally, to meet the above-described need, “alignment marks” have been usually formed along with a pattern for desired circuits and/or elements, thereby measuring the alignment accuracy using the alignment marks.
FIGS. 1 and 2
show an example of the conventional alignment marks of this sort, which is formed on a semiconductor substrate or wafer.
The conventional alignment mark
100
shown in
FIGS. 1 and 2
, which has been usually used for this purpose, comprises two mark elements
118
and
119
. The inner element
119
is located in the outer element
118
. Each of the elements
118
and
119
is square in plan shape. The mark
100
is formed in the following way.
First, as shown in
FIG. 2
, a first layer
122
is formed on the surface of a semiconductor substrate or wafer
121
and then, a patterned resist layer (not shown) is formed on the first layer
122
. The patterned resist layer is formed by the lithography technique. Then, using the patterned resist layer as a mask, the first layer
122
is selectively etched, thereby forming a first or lower circuit pattern (not shown) and the outer square element
118
of the alignment mark
100
in the layer
122
. As clearly seen from
FIG. 2
, the element
118
is a square hole or opening of the layer
122
.
Subsequently, a second layer
123
is formed on the first layer
122
thus patterned so as to contact the bottom and side faces of the outer element
118
(i.e., the hole of the first layer
122
). Then, a resist layer (not shown) is formed on the second layer
123
thus formed, and is patterned by the lithography technique, thereby forming a second or upper circuit pattern (not shown) and the inner square element
119
of the alignment mark
100
on the second layer
123
in the hole
118
of the first layer
122
.
As clearly seen from
FIG. 2
, the inner element
119
of the mark
100
is a square part of the resist layer and located in the hole or outer element
118
. The patterned resist layer thus formed is used as a mask in the next etching process for patterning the underlying second layer
123
.
The alignment mark
110
, shown in
FIG. 3
, comprising the outer and inner elements
118
and
119
thus formed is used to measure the alignment accuracy between the first circuit pattern formed by the first layer
122
and the second circuit pattern of the resist layer. In this case, the relative positional relationship between the outer and inner elements
118
and
119
is measured.
For example, as shown in
FIG. 2
, the distance d
1
between the inner side face
118
a
of the outer element
118
and the facing side face
119
a
of the inner element
119
is measured. At the same time as this, the distance d
2
between the opposite inner side face
118
b
of the outer element
118
and the facing side face
119
b
of the inner element
119
is measured. If the values of the distances d
1
and d
2
are equal, it is judged that the first or lower circuit pattern is overlaid with the second or upper circuit pattern correctly (i.e., with desired alignment accuracy). Sometimes, it is judged whether or not the value of the difference (d
1
−d
2
) between the distances d
1
and d
2
is within a specific range. In any of these cases, no subsequent process is applied unless it is judged that the first or lower circuit pattern is overlaid with the second or upper circuit pattern with desired alignment accuracy.
FIG. 3
shows the layout or arrangement of the conventional alignment marks in an exposure area on a semiconductor wafer. As seen from
FIG. 3
, four alignment marks
110
,
111
,
112
, and
113
are provided in one of rectangular one-shot exposure areas
107
arranged on a semiconductor wafer
10
. Each of the marks
110
,
111
,
112
, and
113
has the same structure as the conventional mark
100
shown in
FIGS. 1 and 2
. Specifically, each of the marks
110
,
111
,
112
, and
113
comprises the square outer and inner mark elements
118
and
119
. The set of the four alignment marks
110
,
111
,
112
, and
113
may be termed the “conventional alignment mark set”.
In the rectangular exposure area
107
in
FIG. 3
, the two marks
110
and
112
are located on the longitudinal, central axis
115
of the area
107
, where the direction along the axis
115
is defined as the Y direction. Since the marks
110
and
112
are on the axis
115
, they are positioned at the middle of the short sides
107
a
and
107
c
of the area
107
. The mark
110
is close to the upper short side
107
a
while the mark
112
is close to the lower short side
107
c
. The other marks
111
and
113
are located on the lateral, central axis
114
of the area
107
, where the direction along the axis
114
is defined as the x direction. Since the marks
111
and
113
are on the axis
114
, they are positioned at the middle of the long sides
107
b
and
107
d
of the area
107
. The mark
111
is close to the right long side
107
b
while the mark
113
is close to the left long side
107
d
. A desired circuit or element pattern (not shown) is typically located among the four marks
110
,
111
,
112
, and
113
in the area
107
.
To measure the alignment accuracy along the X direction, the alignment marks
111
and
113
located on the lateral axis
114
are used. Specifically, the distances d
1
and d
2
between the outer and inner elements
118
and
119
along the X direction is measured for each of the marks
111
and
113
. Then, the difference (d
1
−d
2
) of the distances d
1
and d
2
is calculated. Thus, the alignment accuracy along the X direction is determined by the value of the difference (d
1
−d
2
) thus calculated.
Similarly, the alignment accuracy along the Y direction is measured using the alignment marks
110
and
112
located on the longitudinal axis
115
. Specifically, the distances d
3
and d
4
between the outer and inner elements
118
and
119
along the Y direction is measured for each of the marks
110
and
112
. Then, the difference (d
3
−d
4
) of the distances d
3
and d
4
is calculated. Thus, the alignment accuracy along the Y direction is determined by the value of the difference (d
3
−d
4
) thus calculated.
Actually, a lot of the rectangular exposure areas
107
shown in
FIG. 3
, each of which includes the conventional alignment mark set comprising the four marks
110
,
111
,
112
, and
113
, are regularly arranged on the semiconductor
Le Thoa P
Nelms David
Scully Scott Murphy & Presser
LandOfFree
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